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Oliver D. Patterson
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Proceedings Papers
ISTFA2017, ISTFA 2017: Conference Proceedings from the 43rd International Symposium for Testing and Failure Analysis, 380-385, November 5–9, 2017,
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For a recent replacement metal gate (RMG) technology using a SOI substrate, residue from the dummy gate formed a defect that affected the RMG formation. In this FINFET technology, the high aspect ratio of the gate makes removing the dummy gate very difficult. Residue is left behind, especially in multi-fin structures. This residue was poorly detected by existing Broad-Band-Plasma inspection and thus required Electron Beam Inspection. However, this physical inspection is challenging due to high aspect ratio of the gate and an insulating wafer surface. The defect was verified using TEM, and careful sample prep is shown to be critical to verify the defect. The high aspect ratio and insulating sample in a charged-particle inspection is investigated with Monte-Carlo (MC) simulations.
Proceedings Papers
ISTFA2015, ISTFA 2015: Conference Proceedings from the 41st International Symposium for Testing and Failure Analysis, 205-210, November 1–5, 2015,
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E-beam Inspection (EBI) is used for in-line detection of defects in semiconductor manufacturing. This paper highlights a physical defect mode application where traditional defect inspection techniques, such as broadband plasma and dark field inspection were ineffective in finding the defects of interest. It describes the inspection setup and verification with failure analysis and the application of the technique. This inspection was implemented as a process monitor to detect excursions. The amount of process "ON" time after an etch-chamber part's change was identified as the main factor in MOAT defectivity. The correlation between EBI defect detection and leakage at in-line electrical test was further investigated by looking at each individual die and the leakage associated with the MOAT only. It was observed that the increased leakage could be due to another process factor in the process than a MOAT etch or a MOAT defect that was missed during the EBI inspection.
Proceedings Papers
ISTFA2014, ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis, 241-245, November 9–13, 2014,
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Process defects, either random or systematic, are often the top killers of any semiconductor device. Process defect learning and reduction are the main focuses in both technology development stage and product manufacturing yield ramp stage. In order to achieve fast defect learning, in-line defect inspection is implemented in critical layers during wafer manufacturing. In-line defect inspection is able to detect defects. However, in-line defect inspection alone cannot predict the impact of defects on device functional yield. Failure analysis is an effective method of finding the defects which really cause device functional failures. However, often, the defects found by failure analysis are very different from the original defects, making it difficult to understand the root cause. This paper will describe a methodology how to combine in-line defect inspection and failure analysis together to found the top killer defects and accelerate their root cause identification for fast defect learning and yield improvement.
Proceedings Papers
ISTFA2013, ISTFA 2013: Conference Proceedings from the 39th International Symposium for Testing and Failure Analysis, 494-497, November 3–7, 2013,
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In-line E-beam inspection may be used for rapid generation of failure analysis (FA) results for low yielding test structures. This approach provides a number of advantages: 1) It is much earlier than traditional FA, 2) de-processing isn’t required, and 3) a high volume of sites can be processed with the additional support of an in-line FIB. Both physical defect detection and voltage contrast inspection modes are useful for this application. Voltage contrast mode is necessary for isolation of buried defects and is the preferred approach for opens, because it is faster. Physical defect detection mode is generally necessary to locate shorts. The considerations in applying these inspection modes for rapid failure analysis are discussed in the context of two examples: one that lends itself to physical defect inspection and the other, more appropriately addressed with voltage contrast inspection.
Proceedings Papers
ISTFA2010, ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis, 102-107, November 14–18, 2010,
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This paper introduces a high volume and fast turnaround TEM sample preparation method and requirements for a 300 mm inline DualBeam (FIB/SEM) system with “hands-off” full automation. It requires a factory automation system, robust automated recipes, and an ex-situ TEM lamella liftout system. It describes the recipe structure and TEM lamella lift out procedures. The focus is on fully automated TEM sample preparation for process monitoring in manufacturing line. Two successful examples are described to demonstrate the benefit of this method. The first one is TEM sample for CA profile at M1 level. The second is TEM sample for poly crystalline (PC) line profile at post-etch.
Proceedings Papers
ISTFA2008, ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis, 168-171, November 2–6, 2008,
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Cross-sectional style transmission electron microscopy (TEM) sample preparation techniques by DualBeam (SEM/FIB) systems are widely used in both laboratory and manufacturing lines with either in-situ or ex-situ lift out methods. By contrast, however, the plan view TEM sample has only been prepared in the laboratory environment, and only after breaking the wafer. This paper introduces a novel methodology for in-line, plan view TEM sample preparation at the 300mm wafer level that does not require breaking the wafer. It also presents the benefit of the technique on electrically short defects. The methodology of thin lamella TEM sample preparation for plan view work in two different tool configurations is also presented. The detailed procedure of thin lamella sample preparation is also described. In-line, full wafer plan view (S)TEM provides a quick turn around solution for defect analysis in the manufacturing line.
Proceedings Papers
ISTFA2007, ISTFA 2007: Conference Proceedings from the 33rd International Symposium for Testing and Failure Analysis, 270-274, November 4–8, 2007,
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A methodology for detecting silicide pipes on SOI technology in-line soon after their formation is described. Techniques currently exist to detect pipes in-line, but only much later in the process. This methodology, which is based on voltage contrast inspection of test structures, allows experiments to be completed more quickly providing much faster cycles of learning. Two different test structures are described. The first one was designed for other purposes but was adopted for silicide pipe detection at M1. The second was specially designed and allows pipe detection at silicide anneal, W CMP and M1. A procedure for determining the cause of buried shorts detected by the eS32 is also described. Experimental results are presented to demonstrate the benefit of this technique.
Proceedings Papers
ISTFA2005, ISTFA 2005: Conference Proceedings from the 31st International Symposium for Testing and Failure Analysis, 401-406, November 6–10, 2005,
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This paper shows that in-line voltage contrast inspection can be used to monitor and debug mechanisms causing via and contact opens using ungrounded chain test structures. This opens up a large number of new opportunities to the benefits of in-line VC inspection. A theory explaining the VC appearance of a broken chain is proposed and experimentally verified. The methodology used at IBM’s 300mm fab to apply this phenomenon is described along with some use cases.
Proceedings Papers
ISTFA2004, ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis, 414-418, November 14–18, 2004,
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In-line repair of same-level killer defects is suggested as a method of the future for achieving higher yields. A methodology describing selection of killer defects and how to repair them is presented. A proof of concept experiment is presented where killer defects are removed from comb test structures using a FIB. An economic analysis is also included which indicates that this technique is economically viable for more costly chip designs. Therefore additional development work is merited.
Proceedings Papers
ISTFA2002, ISTFA 2002: Conference Proceedings from the 28th International Symposium for Testing and Failure Analysis, 591-598, November 3–7, 2002,
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Electrical failures due to front-end defectivity may be detected in-line using large area PVC inspection. Application of this method to a self-aligned contact module of a memory chip is presented. Most of the defectivity affecting this module is non-visual. The PVC inspection results allow representative defects to be cross-sectioned and fully characterized soon after they are created. This approach to FA offers much faster results and much larger sampling of the defectivity affecting each lot than end of line FA. Current experiments to debug the principal defect types are described.