In critical fields such as automotive, medicine, and defense, ensuring the reliability of microelectronics has been paramount given the extensive nature of their globalized supply chain. Automated visual inspection (AVI) of printed circuit boards (PCBs) offers a solution through computer vision and deep learning to automate defect detection, component verification, and quality assurance. In this paper, our research follows this precedent by introducing a novel dataset and annotations to train artificial intelligence (AI) models for extracting PCB connectivity components. Utilizing high-resolution images, and state-of-the-art instance segmentation models, this study aims to examine the difficulties in this implementation and lay the groundwork for more robust automated visual inspection.

Due to the continuous outsourcing of printed circuit board (PCB) fabrication, PCB counterfeits and Trojans have increased by a significant margin, and this has necessitated rapid and advanced hardware assurance techniques. PCB Image segmentation is the primary step in PCB assurance. Over the years, few PCB component segmentation methods have been proposed and none of those have provided a definite benchmark of performance. Besides those methods haven’t discussed how the performance is correlated with underlying data or annotation quality. In this work, we present a benchmark on PCB image segmentation along with a high-quality dataset. In addition, we explore how annotation quality affects component segmentation and present possible future research directions to work with coarse annotations to alleviate the human effort behind full data annotation tasks. We have analyzed the performance of the preferred Deep Neural Network (DNN) architecture with the data annotation quality and presented the direction to leverage the outcome with limited quality annotations. Finally, we present the qualitative as well as the quantitative results to demonstrate the performance of our techniques and provide observations and future research directions on the overall task.

The increasing demand for semiconductor chips and the outsourcing of chip fabrication have heightened vulnerability to hardware security threats. While optical probing has been used extensively for semi-invasive/non-invasive attacks, its resolution limits and obsolescence in advanced technologies have necessitated exploring other techniques. Electron-beam probing (EBP) has emerged as a powerful method, offering 20x better spatial resolution than optical probing, and applies to sub- 7nm flip-chips and advanced 3D architecture systems. However, the increased resolution of EBP also poses a threat to sensitive information on these advanced chips, calling for developing countermeasures to secure assets. By understanding the capability of EBP, the potential of using EBP to extract sensitive data such as encryption keys, soft IP, neural network parameters, and proprietary algorithms will be discussed. This paper delves into the principles behind EBP, its capabilities, challenges for this technique, and potential applications in failure analysis and potential attacks. It highlights the need for developing effective countermeasures to protect sensitive information on advanced node technologies.

Hardware obfuscation is a proactive design-for- trust technique against integrated circuit (IC) supply chain threats, i.e., intellectual property (IP) piracy and overproduction. Many studies have evaluated numerous obfuscation techniques, broadly classified as IC camouflaging, logic locking, and split manufacturing. In split manufacturing, threats introduced by an untrusted foundry are eliminated by manufacturing only the front-end of line (FEOL) layers in the high-end untrusted foundry, and back-end of line (BEOL) layers in the design house’s trusted low-end foundry to hide BEOL connections from the untrusted foundry. However, researchers proposed several attacks based on physical layout design heuristic, network-flow model, and placement-routing proximity to extract missing back-end of line connections. Nevertheless, split manufacturing suffers from yield due to challenges in properly aligning FEOL connections with the BEOL. This paper proposes LLE, which protects ICs from piracy and reverse-engineering by untrusted foundries. In this approach, we perform layout-level obfuscation by creating an intermediate metal layer mesh to obscure the BEOL connections from the FEOL. After fabrication from an untrusted foundry, the mesh can be edited using a focused-ion beam (FIB) editing tool in a trusted facility (e.g., FIB lab) to realize the actual inter- connection. Hence, unlike split manufacturing, LLE eliminates the requirement of a separate trusted foundry and establishes trust in the microelectronic supply chain by lowering cost and yield loss. To validate the effectiveness of LLE, we fabricated a test chip in MITLL Low- Power FDSOI CMOS Process. In the silicon test chip, we demonstrate that LLE can prevent IC piracy and reverse engineering with low costs and yield losses in the semiconductor supply chain.

IC camouflaging has been proposed as a promising countermeasure against reverse engineering. Camouflaged gates contain multiple functional device structures, but appear as a single layout under microscope imaging, thereby concealing circuit functionality. The recent covert gate camouflaging design comes with a significantly reduced overhead cost, allowing numerous camouflaged gates in circuits which improves resiliency against invasive and semi-invasive attacks. Dummy inputs are used in the design, but SEM imaging analysis has only been performed on simplified contact structures so far. In this study, we fabricated real and dummy contacts in different structures and performed a systematic SEM analysis to investigate contact charging and passive voltage contrast. Machine learning based pattern recognition was also employed to examine the possibility of differentiating real and dummy contacts. Based on our experimental results, we found that the difference between real and dummy contacts is insignificant, which effectively prevents SEM-based reverse engineering.