This paper discusses advancements that have been made in scanning microwave impedance microscopy (sMIM) and how they are being used to measure various electrical properties in semiconductor devices. It explains that sMIM has a sensitivity of less than 0.1 aF and can measure minute changes in dielectric constant (k-value) and distinguish dopant levels over a wide range of concentrations with a spatial resolution of a few nm. For dielectric films and dopant levels, measurements are conveniently given in log-linear form with a repeatability well within the typical requirements for process monitoring. This, in turn, has enabled reliable quantification, where once only qualitative information was provided. The paper presents real-device results representing a wide range of measurement scenarios.

Two-beam systems (focused ion beam (FIB) integrated with a scanning electron microscope (SEM)) have enabled site-specific analysis at the nano-scale through in situ “mill and view” capability at high resolution. In addition, a FIB-SEM can be used to cut away a lamella from a bulk sample and thin it for transmission electron microscopy (TEM) imaging. We studied the temperature dependence of FIB milling on compound semiconductors and thin films such as copper that are used in integrated circuits. These materials (GaAs, GaN, InN, etc) react chemically and physically with the gallium in the FIB and change chemical composition and may also change morphology. Copper metallization of IC’s has been difficult to mill without undesirable side effects. FIB milling for analysis of these materials becomes difficult if not impossible. Since temperature can be a big factor in chemical and physical reactions we investigated this and report here the effect of cooling the sample to cryogenic temperatures while milling. In addition, we report on the development of a process to prepare TEM lamellae with FIB entirely in a cryogenic environment.

The ability to edit a circuit in silicon quickly and confidently is extremely valuable as it permits verification of changes or fixes without the need to generate new reticles and fabricate new silicon. However, dramatic changes in the material used in IC’s combined with the downward scaling of dimensions required the development of a scalable process not only in three dimensions but also in material. Details of this process and results are presented in this paper.

Secondary electron signal is widely used in Focused Ion Beam (FIB) systems for imaging and endpointing. In the application of integrated circuit modification, technology has progressed towards smaller dimensions and higher aspect ratios. Therefore, FIB based circuit modification processes require the use of primary ion beam currents below 10 pA and Gas Assisted Etching (GAE). At low beam currents, short pixel dwell times and high aspect ratios, the level of available secondary electrons for detection has declined significantly. FIB GAE and deposition requires delivery and release of a gaseous agent near the beam scanning area, and involves insertion of a gas delivery nozzle made of conductive material and grounded for charge prevention purposes. The proximity of a grounded gas delivery nozzle to the area being milled and/or imaged creates a “shielding” effect, further lowering secondary electron signal level. The application of a small positive bias to the gas delivery nozzle provides an effective way of reducing the “shielding” effect. Depending on the geometrical arrangement of the gas delivery system and other conductive objects in the chamber, an optimized nozzle bias potential can create conditions favorable for enhanced extraction and collection of secondary electrons. The level of the secondary electron image signal, collected in an FEI Vectra 986+ system, from a grounded copper sample with the nozzle extended and biased can be enhanced as much as six times as compared to the grounded nozzle. Secondary electron intensity endpoint is improved on backside samples, however shielding of the nozzle field by the bulk silicon substrate limits the electron extraction effect from within a via. For front side edits the improvement of endpoint signal level can be dramatic. Lateral image offset induced by the electrostatic field of a biased nozzle, can be removed by software position compensation.

As semiconductor device manufacturing technologies move below the 100 nm node constrains on using Focused Ion Beam (FIB) systems to perform circuit edit operations tighten dramatically. Phenomena associated with via milling and deposition processes, considered minor side effects in the past, may become performance-limiting factors. Obstacles, associated with editing deep sub micron technologies beyond 100nm node, which include navigational accuracy, beam placement stability, and small via milling and filling processes, cannot be completely overcome without advances in overall FIB system performance and operation. We present a detailed technical overview of the challenges, associated with silicon microsurgery on devices, manufactured with sub 100 nm process technology and describe recent advancements in FIB technology and techniques which address these areas and allow successful modification of today’s most advanced designs.

Advances in FIB (focused ion beam) chemical processes and in the Ga (gallium) beam profile are discussed; these advances are necessary for the successful failure analysis, circuit edit and design verification of advanced, sub-0.13µm Cu devices. Included in this article are: a novel FIB method (CopperRx) for smoothly milling thick, large grained Cu lines; H2O and O2 processes for cleanly cutting thin, smaller grained Cu lines, thereby forming electrically open interconnects; a XeF2 GAE (gas assisted etching) process for etching low k, CVD dielectrics such as F and C doped SiO2; H2O and XeF2 GAE processes for etching low k, spin-on, organic dielectrics such as SiLK; a recently developed recipe for the deposition of SiO2 based material with intermediate resistivity (10 6 µohm·cm) which is useful in the design verification of frequency sensitive, high speed analog and SOC (system on chip) circuits; an improved, more Gaussian Ga beam with less current density in the beam tails (VisION column) which provides higher resolution, real time images needed for end-point detection on sub 0.13µm features during milling.

While integrated circuits are routinely modified using Focused Ion Beam systems (FIB), the reliability of these modifications has not yet been thoroughly studied. For several years, researchers at Sandia National Labs and CNES have been involved in the evaluation of the impact of FIB exposure on semiconductor structures. We have all come to the same conclusion: the intrinsic behavior of a circuit is altered after FIB intervention and the damage cannot be completely recovered but can be controlled. Despite these results, modified circuits are used in many applications such as satellites or even more critical environments. Although FIB modifications are invasive to the circuit they provide a working sample that can prove out, in silicon, a design change. However, is the functionality of FIB modified ICs reliable? In more practical terms: Can we use modified devices for our applications and what guarantee do we have that they will work after a few months? To answer these questions, we have conducted extended studies addressing both MOS and bipolar circuits. We used basic structures (such as transistors and diodes) and complex structures (operational amplifiers, oscillators, etc) and studied the effects of two different FIB systems, a Schlumberger P2X and an FEI Vectra 986. We have investigated the reliability of the devices by monitoring intrinsic parameters, before FIB, after FIB, during life testing and after life testing.

We report on recent studies of the effects of 50 keV focused ion beam (FIB) exposure on MOS transistors. We demonstrate that the changes in transistor parameters (such as threshold voltage, Vt) are essentially the same for exposure to a Ga+ ion beam at 30 and 50 keV under the same exposure conditions. We characterize the effects of FIB exposure on test transistors fabricated in both 0.5 μm and 0.225 μm technologies from two different vendors. We report on the effectiveness of overlying metal layers in screening MOS transistors from FIB-induced damage and examine the importance of ion dose rate and the physical dimensions of the exposed area.

Both the increased complexity of integrated circuits, resulting in six or more levels of integration, and the increasing use of flip-chip packaging have driven the development of integrated circuit (IC) failure analysis tools that can be applied to the backside of the chip. Among these new approaches are focused ion beam (FIB) tools and processes for performing chip edits/repairs from the die backside. This paper describes the use of backside FIB for a failure analysis application rather than for chip repair. Specifically, we used FIB technology to prepare an IC for inspection of voided metal interconnects (“lines”) and vias. Conventional FIB milling was combined with a superenhanced gas assisted milling process that uses XeF2 for rapid removal of large volumes of bulk silicon. This combined approach allowed removal of the TiW underlayer from a large number of M1 lines simultaneously, enabling rapid localization and plan view imaging of voids in lines and vias with backscattered electron (BSE) imaging in a scanning electron microscope (SEM). Sequential cross sections of individual voided vias enabled us to develop a 3D reconstruction of these voids. This information clarified how the voids were formed, helping us identify the IC process steps that needed to be changed.

The increasing use of flip-chip packaging is challenging the ability of conventional Focused Ion Beam (FIB) systems to perform even the most basic device modification and debug work. The inability to access the front side of the circuit has severely reduced the usefulness of traditional micro-surgery. Advancements in FIB technology and its application now allow access to the circuitry from the backside through the bulk silicon. In order to overcome the problem of imaging through thick silicon, a microscope with Infra Red (IR) capability has been integrated into the FIB system. Navigation can now be achieved using the IR microscope in conjunction with CAD. The integration of a laser interferometer stage enables blind navigation and milling with sub-micron accuracy. To optimize the process, some sample preparation is recommended. Thinning the sample to a thickness of about 100 µm to 200 µm is ideal. Once the sample is thinned, it is then dated in the FIB and the area of interest is identified using the IR microscope. A large hole is milled using the FIB to remove most of the silicon covering the area of interest. At this point the application is very similar to more traditional FIB usage since there is a small amount of silicon to be removed in order to expose a node, cut it or reconnect it. The main differences from front-side applications are that the material being milled is conductive silicon (instead of dielectric) and its feature-less and therefore invisible to a scanned ion beam. In this paper we discuss in detail the method of back-side micro-surgery and its electron device performance. Failure Analysis (FA) is another area that has been severely limited by flip-chip packaging. Localized thinning of the bulk silicon using FIB technology offers access to diagnosing failures in flip-chip assembled parts.