In this paper, a zero yield case relating to a systematic defect in N+ poly/N-well varactor (voltage controlled capacitor) on the RF analog circuitry will be studied. The systematic problem solving process based on the application of a variety of FA techniques such as TIVA, AFP current Imaging and nano-probing, manual layout path tracing, FIB circuit edit, selective etching together with Fab investigation is used to understand the root cause as well as failure mechanism proposed. This process is particularly critical for a foundry company with restricted access to data on test condition setup to duplicate the exact failure as well as no layout tracing available at time of analysis. The systematic defect was due to gate oxide breakdown as a result of implanter charging. It serves as a good reference to other wafer Fabs encountering such an issue.

In this paper, a comprehensive analysis methodology for gate oxide integrity (GOI) failure using combined FA techniques is proposed. The current method integrates the failure analysis flow we previously reported with a new flow proposed in this paper. The method is applicable to a wide range of GOI failure cases and has been used in analyzing many product wafers with GOI failure. In particular, there is one wafer with GOI failure that results from known failed process machines. This wafer could be readily analyzed with this new method to identify the root causes. The newly proposed flow is based on our previous report on GOI failure analysis, but the detection limit of contamination elements was significantly improved. The enhancement of detection limit is mainly attributable to the utilization of Vapor Phase Decomposition and Inductively Coupled Plasma Mass Spectrometry (VPD ICP-MS). The ICP-MS technique is highly sensitive and capable of simultaneously measuring a large number of elements at very low concentration level in the range of ppb (part per billion) to ppt (part to trillion). This enhanced sensitivity enables effective investigation of contamination caused by specific machines. A case study of GOI failure investigated by the proposed new method will be discussed in detail. In the study, Al, Fe, Mo and Sn contamination from a suspected tool were detected by ICPMS, followed by confirmation by Secondary Ion Mass Spectrometry (SIMS) on the affected product wafers. Failurepart isolation investigations of the affected diffusion furnace revealed that the root cause of the failure is due to a defective gas flow valve.

In this paper, a low yield case relating to a systematic array of failures in a ring pattern due to ADC_PLL failures on low yielding wafers will be studied. A systematic problem solving process based on the application of a variety of FA techniques such as TIVA, AFP current imaging, layout path tracing, PVC and XTEM together with Fab investigation is used to understand the root cause as well as failure mechanism proposed. This process is particularly critical in a wafer foundry in which there is minimal available data on the test condition setup to duplicate the exact failure. The ring pattern was due to systematically open via as a result of polymer built-up from plasma de-chuck issue. It would serve as a good reference for a wafer Fab that encounters such an issue.