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1-3 of 3
Nelson Gomez
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Proceedings Papers
ISTFA2023, ISTFA 2023: Conference Proceedings from the 49th International Symposium for Testing and Failure Analysis, 403-410, November 12–16, 2023,
Abstract
View Papertitled, Multilayer pFIB Trenches for Multiple Tip EBAC/EBIRCH Analysis and Internal Node Transistor Characterization
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for content titled, Multilayer pFIB Trenches for Multiple Tip EBAC/EBIRCH Analysis and Internal Node Transistor Characterization
In this work, we present three case studies that highlight the novelty and effectiveness of using multiple plasma FIB trenches to simultaneously access multiple metal layers for nanoprobing failure analysis. Multilayer access enabled otherwise impossible two-tip current imaging techniques and allowed us to fully characterize suspect logic gate transistors by exposing internal nodes, while preserving higher metal inputs and outputs. The presented case studies focus on late node planar and established FinFET technologies. The delayering techniques used are not necessarily technology dependent, but highly scaled and advanced processes generally require smaller trench areas for multilayer access. The minimum trench dimensions are limited by ion beam imaging resolution and trench-nanoprobe tip geometry.
Proceedings Papers
ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 381-387, November 10–14, 2019,
Abstract
View Papertitled, Nanoprobing of Advanced Silicon-On-Insulator Transistors
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for content titled, Nanoprobing of Advanced Silicon-On-Insulator Transistors
As advanced silicon-on-insulator (SOI) technology becomes a more widespread technology offering, failure analysis approaches should be adapted to new device structures. We review two nanoprobing case studies of advanced SOI technology, detailing the electrical characterization of a compound gate-to-drain defect as well as the characterization of unexpected SOI source-to-well leakage.
Proceedings Papers
ISTFA2018, ISTFA 2018: Conference Proceedings from the 44th International Symposium for Testing and Failure Analysis, 309-314, October 28–November 1, 2018,
Abstract
View Papertitled, A Case Study of High SRAM Low Power Mode Current
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for content titled, A Case Study of High SRAM Low Power Mode Current
Low power mode current is a very important parameter of most microcontrollers. A non-production prototype microcontroller had high current issues with certain SRAM modules which were produced using a new memory compiler. All devices were measuring 100’s μA of low power mode current which was an order of magnitude higher than the requirement. Many failure analysis (FA) techniques had to be used to determine the root cause: Optical Beam Induced Resistance Change (OBIRCh), photo emission microscopy (PEM), microprobing, and nanoprobe device characterization. Transistor models and measurements of probe structures from the effected lots both predicted that the device low power mode current would meet expectations; however, all first silicon samples had elevated low power mode current. A knowledge of low power design methodology was needed to ensure all issues were discovered.