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Neel Leslie
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Proceedings Papers
ISTFA2024, ISTFA 2024: Conference Proceedings from the 50th International Symposium for Testing and Failure Analysis, 519-522, October 28–November 1, 2024,
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This paper demonstrates that e-beam assisted device alteration (EADA) is a powerful, high-resolution technique for fault isolation debug for advanced technology nodes. A case study using this technique is reviewed and shows successful isolation of a defective single inverter. In addition, fundamental studies of ring oscillator behavior and device perturbations with e-beam exposure found clear correlations for electron beam exposure with NMOS/PMOS device parameters. Electron-hole pair generation in the device with beam exposure is likely the main component for the perturbation, but there may be other contributing factors including charging effects and/or heating.
Proceedings Papers
ISTFA2023, ISTFA 2023: Conference Proceedings from the 49th International Symposium for Testing and Failure Analysis, 164-167, November 12–16, 2023,
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With the introduction of flip-chip technology, optical-based failure analysis techniques have played a critical role in many failure analysis (FA) laboratories. This is due to the unhindered access for photons to probe or emit from the transistor layer through the bulk silicon. Among the optical techniques, laser voltage imaging (LVI) and laser voltage probing (LVP), collectively called LVx, dominate because they directly expose the electrical activity of a given circuit or cell.
Journal Articles
Journal: EDFA Technical Articles
EDFA Technical Articles (2023) 25 (4): 28–34.
Published: 01 November 2023
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A scanning electron microscope system measures voltage contrast on device-under-test surfaces. This article addresses a limited set of applications that rely on voltage contrast (VC) measurements in SEM systems, showing how VC measurements can probe electrical activity running at speeds as high as 2 GHz on modern active integrated circuits.
Proceedings Papers
ISTFA2022, ISTFA 2022: Conference Proceedings from the 48th International Symposium for Testing and Failure Analysis, 120-124, October 30–November 3, 2022,
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Infrared lock-in thermography systems are frequently utilized for non-destructive failure analysis of integrated circuits due to sensitivity of the thermal detector to small temperature changes from electrical activity. This thermal sensitivity can also be leveraged for design verification and debug of device thermal management via absolute temperature mapping. The application of temperature mapping to a device under test (DUT) that requires boards and sockets, such as in tester based applications, has traditionally been challenging, due to the requirement that the DUT not be moved and the difficulty of heating the DUT through the thermal mass of the boards and sockets to which the DUT is mounted. This paper describes a proposed alternative single-temperature in-situ calibration method to eliminate the need for a heated thermal chuck for absolute temperature mapping. Preliminary results are promising and show that the new alternative single-temperature in-situ method results in temperature measurements within 1 °C close to room temperature and within 2.5 °C at elevated temperatures up to approximately 75 °C, as compared to the 1 °C accuracy of the current standard two-temperature in-situ method. While this alternate method is not as accurate as the standard two-temperature in-situ calibration method, the fact that it can be performed at a single room temperature means that it enables absolute temperature mapping for use cases requiring boards or socketed DUTs, as is the case for tester applications. An example characterization of a DUT utilizing varying clock signal inputs shows the added flexibility and ease of setup that the alternative single-temperature workflow brings, creating new opportunities for use-cases such as boards and testers where the use of a heated thermal chuck is not viable.
Proceedings Papers
ISTFA2022, ISTFA 2022: Conference Proceedings from the 48th International Symposium for Testing and Failure Analysis, 125-128, October 30–November 3, 2022,
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Recently, electron beam probing (EBP) has had a resurgence in failure analysis communities due to its clear resolution advantage compared to optical techniques. This paper describes an approach for a detailed advanced logic e-beam probing system, capable of measuring both high bandwidth waveforms and frequency maps. An investigation of optimizing the signal-to-noise of the pulsed beam is presented. By minimizing the working distance and the use of quadrature signal analysis, the e-beam prober is capable of high bandwidth and high-resolution data with adequate signal-to-noise. The use of such system provides a scalable solution for electrical failure analysis for advanced logic integrated circuits.
Proceedings Papers
ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 305-310, November 15–19, 2020,
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In a previous study, the authors introduced a novel technique of using low-beam energy Gallium Focused Ion Beam to expose a large area of Shallow Trench Isolation (STI) over a Dynamic Ring Oscillator (DRO) incurring virtually no change of its operating frequency. In this paper, the authors further investigate the influence of extended dose delivery of 5 kV Ga+ after the initial exposure of the STI over a DRO on modern 7 nm process. The motivation of this study is to understand the dynamics between the Ga+ ion interaction at lower beam energies on live and functional devices and the failure mechanism of the device from such interaction. The frequency of the DROs after the initial STI exposure at 5 kV exhibits <1% increase. Additional dosage of lowkV exposure was performed over the exposed STI and its effects on the DRO frequency was monitored. Finally TEM analysis of the irradiated DROs will be analyzed to understand the failure mechanism of transistors.
Proceedings Papers
ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 12-16, November 15–19, 2020,
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Correlation across applications and imaging platforms is essential and brings increased insurance for fault isolation in advance of destructive imaging. This paper demonstrates an approach for a detailed advanced packaging defect isolation and analysis workflow. To determine the effectiveness of the proposed workflow, a 28nm flip-chip was used as a test vehicle. By using this workflow, the yield in determining the fault location has increased from 60% to over 85%. To further improve the result, a surface charging mitigation scheme was used and the resulting measured correlative offset between the two systems was found to be less than 10um. This creates novel opportunities in reducing the size of the cross-section and increasing the overall throughput to find the defect, with high confidence. This workflow creates unique abilities in fault localization and analysis as it can detect both opens and shorts between the different techniques that are employed.
Proceedings Papers
ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 116-121, November 15–19, 2020,
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Working on wafer-level has been the only way of performing electrical failure analysis (EFA) without the need for die-packaging. The introduction of Si-interposer based 2.5D packaging, with high bandwidth memory (HBM) stacks surrounding our GPU chip, drastically increasing packaging turn around times from approximately 3 days to 3-4 weeks. Having to wait more than 3 weeks for EFA and debug work of 1st Silicon chips is a significant risk for chip bring-up. To address these challenges, this paper presents different ways of reusing the existing wafer-level EFA tool for single die EFA, and introduces a concept for a novel and dedicated single die tool. Additionally, singulated die fixturing and support windows are designed to enable the usage of a 2.45 Numerical Aperture Solid Immersion Lens, and first results from a near reticle limited 16 nm Fin-FET GPU product are also presented.
Proceedings Papers
ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 330-334, November 15–19, 2020,
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OBIRCh(Optical Beam Induced Resistance Change) and TIVA (Thermal Induced Voltage Alteration) are widely used ElectricalFailure Analysis techniques for finding defects under static conditions. This paper will discuss the requirements for a good amplifier to be used for OBIRCh, and recent improvements that have been released to market from Thermo Fisher Scientific.
Proceedings Papers
ISTFA2018, ISTFA 2018: Conference Proceedings from the 44th International Symposium for Testing and Failure Analysis, 334-338, October 28–November 1, 2018,
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In high numerical aperture (NA) subsurface imaging, we can obtain higher resolution in selected directions at the expense of resolutions in other directions, utilizing the vectorial properties of polarized light. In this work, we propose an image fusion framework that produces a single image with higher resolution and image quality in all directions by processing multiple images acquired by varying the polarization direction of the linearly polarized input laser light.
Proceedings Papers
ISTFA2017, ISTFA 2017: Conference Proceedings from the 43rd International Symposium for Testing and Failure Analysis, 201-206, November 5–9, 2017,
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Visible light probing (VLP) introduced significant spatial resolution improvement by decreasing the wavelength beyond 1064nm. VLP requires thinning the device backside below 10micrometer. Once this challenge is addressed, questions arise regarding invasiveness: how does the laser affect the transistor performance, and how is this manifest in LVx (laser voltage imaging and laser voltage probing) measurements. This paper addresses these questions using a 785nm VLP system. The results are compared with those of 1320nm, 1154nm, and 1064nm when pertinent. It is concluded that changing wavelengths from the traditional 1320nm LVx laser to the visible 785nm laser provides a 40% resolution improvement. Fortunately, decreasing the incident 785nm power eliminates obvious signs of charge-carrier effects. Furthermore, the rise-time is not affected by the laser when measured from the gate.
Proceedings Papers
ISTFA2016, ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis, 32-37, November 6–10, 2016,
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LVx, a workhorse in many failure analysis laboratories, consists of laser voltage imaging (LVI) and laser voltage probing. Laser voltage tracing (LVT) eliminates the inherent restrictions bestowed by LVI and reduces the need for costly probing. It monitors a distinct feature of the test pattern and creates a corresponding signal map. This weapon in the LVx arsenal significantly decreases debug time and will prove as invaluable as LVI. Beginning with an overview of the limitations of traditional LVx, this paper provides information on the process steps, experimental setup, and applications of LVT. LVT introduces a new approach to monitoring LVx signals. The most obvious LVT application is debugging problematic peripheral NAND circuitry.