Hardware obfuscation is a proactive design-for- trust technique against integrated circuit (IC) supply chain threats, i.e., intellectual property (IP) piracy and overproduction. Many studies have evaluated numerous obfuscation techniques, broadly classified as IC camouflaging, logic locking, and split manufacturing. In split manufacturing, threats introduced by an untrusted foundry are eliminated by manufacturing only the front-end of line (FEOL) layers in the high-end untrusted foundry, and back-end of line (BEOL) layers in the design house’s trusted low-end foundry to hide BEOL connections from the untrusted foundry. However, researchers proposed several attacks based on physical layout design heuristic, network-flow model, and placement-routing proximity to extract missing back-end of line connections. Nevertheless, split manufacturing suffers from yield due to challenges in properly aligning FEOL connections with the BEOL. This paper proposes LLE, which protects ICs from piracy and reverse-engineering by untrusted foundries. In this approach, we perform layout-level obfuscation by creating an intermediate metal layer mesh to obscure the BEOL connections from the FEOL. After fabrication from an untrusted foundry, the mesh can be edited using a focused-ion beam (FIB) editing tool in a trusted facility (e.g., FIB lab) to realize the actual inter- connection. Hence, unlike split manufacturing, LLE eliminates the requirement of a separate trusted foundry and establishes trust in the microelectronic supply chain by lowering cost and yield loss. To validate the effectiveness of LLE, we fabricated a test chip in MITLL Low- Power FDSOI CMOS Process. In the silicon test chip, we demonstrate that LLE can prevent IC piracy and reverse engineering with low costs and yield losses in the semiconductor supply chain.