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1-3 of 3
Nagesh Tamarapalli
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Proceedings Papers
ISTFA2011, ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis, 98-102, November 13–17, 2011,
Abstract
View Papertitled, Debugging an Invisible Flaky Scan Chain Defect
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for content titled, Debugging an Invisible Flaky Scan Chain Defect
In general, scan shift failures are difficult to debug. Usually we use the compressed-mode chain test or scan capture-based chain diagnosis to ascertain the small chain segment or the position of the sequential element in the chain that is the cause of the failure. This method of diagnosis works well when the failures are static and limited to a chain segment, but fails to give results when the failure is caused by intra chain or inter chain segment interactions. This paper presents a scenario in which the root cause of the chain failures was due to interaction between chains. We call it the “invisible flaky chain defect” because -- although we were able to replicate failure at a test point (voltage-frequency) on the Shmoo -- the failing cycles changed from run to run.
Proceedings Papers
ISTFA2006, ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis, 412-418, November 12–16, 2006,
Abstract
View Papertitled, Yield Learning with Layout-aware Advanced Scan Diagnosis
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for content titled, Yield Learning with Layout-aware Advanced Scan Diagnosis
Manufacturing yield is stable when the technology is mature. But, once in a while, excursions may occur due to variances in the large number of tools, materials, and people involved in the complex IC fabrication. Quickly identifying and correcting the root causes of yield excursions is extremely important to achieving consistent, predictable yield, and maintaining profitability. This paper presents a case study of yield learning through a layout-aware advanced scan diagnosis tool to resolve a significant yield excursion for an IC containing 1 Million logic gates, manufactured at 130 nm technology node.
Proceedings Papers
ISTFA2005, ISTFA 2005: Conference Proceedings from the 31st International Symposium for Testing and Failure Analysis, 501-509, November 6–10, 2005,
Abstract
View Papertitled, Advanced Scan Diagnosis Based Fault Isolation and Defect Identification for Yield Learning
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for content titled, Advanced Scan Diagnosis Based Fault Isolation and Defect Identification for Yield Learning
Yield analysis of sub-micron devices is an ever-increasing challenge. The difficulty is compounded by the lack of in-line inspection data as many companies adopt foundry or fab-less models for acquiring wafers. In this scenario, failure analysis is increasingly critical to help drive yields. Failure analysis is a process of fault isolation, or a method of isolating failures as precisely as possible followed by identification of a physical defect. As the number of transistors and metal layers increase, traditional fault isolation techniques are less successful at isolating a cause of failures. Costs are increasing due to the amount of time needed to locate the physical defect. One solution to the yield analysis problem is scan diagnosis based fault isolation. Previous scan diagnosis based techniques were limited with little information about the type of fault and confidence of diagnosis. With new scan diagnosis algorithms it is now possible to not only isolate, but to identify the type of fault as well as assigning a confidence ranking prior to any destructive analysis. This paper presents multiple case studies illustrating the application of scan diagnosis as an effective means to achieve yield enhancement. The advanced scan diagnostic tool used in this study provides information about the fault type as well as fault location. This information focuses failure analysis efforts toward a suspected defect, decreasing the cycle time required to determine root cause, as well as increasing the over all success rate.