As the DRAM structure is miniaturized, the cell capacitance is reduced and resistance is increased. Because of this change, the DRAM operation is more sensitive than previous generations to changes of the device elements. The device elements consist of cell capacitance, Bit Line (BL) capacitance, cell node resistance, supply-voltage and the surround noise. The elements were changed by decreasing the cell node dimensions. The write time (tWR) is degraded by changing the elements. In particular, the noise is very variable element on change of surrounding cell phase which is data1 or data 0. In this paper, we show that one of the most dominant contributors to failure is the plate noise and explain how plate voltage level affects tWR delay. The effect of the plate voltage modulation can be correlated with ∆Vbl which is bit line level difference to read out the data. We define this phenomenon as the plate dc noise effect and propose a model in miniaturized DRAM.

The open bit line architecture scheme is an effective method to achieve higher density memory devices. With the scaling of DRAM, we have adopted a bit line sense amplifier (BLSA) design using a shared local power line for reducing the circuit layout dimensions. As a result of this new design, the write time of the memory cell was sometimes degraded because of an increase in initial sensing noise. This paper gives a detailed analysis of the problem caused by the initial sensing noise by examination of the behaviour of the opposite data portion of the cell array matrix when the word line is not activated. Finally, we propose a design improvement to reduce the magnitude of noise peaks and the results of this improvement when implemented in the test vehicle.