The back-end-of-line (BEOL) structure of current IC devices fabricated for advanced technologies is composed of film stacks with multiple interfaces. The requirement of high interfacial strength is therefore necessary between the different layers in the BEOL stacks to ensure device reliability. To enhance the IC performance for new technologies, inter-level dielectric (ILD) made of SiO2 is replaced by low-k and ultra low-k (ULK) dielectrics, which possess a low dielectric constant but have poor mechanical strength. Therefore, the challenge in maintaining BEOL film stack integrity and reliability becomes even greater for advanced technologies. In this paper, we show failure analysis results on a case study of ULK adhesion failure during the IC manufacturing process. The symptoms of the BEOL failure are due to debris dropping on the wafer during chemical mechanical polishing (CMP) after Cu thin film deposition and failure of focusing at wafer extreme edge during the subsequent photolithography process. Extensive mechanical and chemical analyses were conducted on the ULK and adjacent thin films. It was revealed that the interface of ULK and Silicon Nitride from a suspected problematic machine showed abnormally low adhesion energy and high carbon composition. Troubleshooting on that suspected machine found a clog in the foreline. Based on the failure analysis and machine troubleshooting results, the failure mechanism of the case was discussed.

Electron-beam induced radiation damage can give rise to large structural collapse and deformation of low k and ultra low k IMD in semiconductor devices, posing great challenges for failure analysis by electron microscopes. Such radiation damage has been frequently observed during both sample preparation by dual-beam FIB and TEM imaging. To minimize radiation damage, in this work we performed systematic studies on every possible failure analysis step that could introduce radiation damage, i.e., pre-FIB sample preparation, FIB milling, and TEM imaging. Based on these studies, we utilized comprehensive technical solutions to radiation damage by each failure analysis step, i.e., low-dose/low-kV FIB and low-dose TEM techniques. We propose and utilize the low-dose TEM imaging techniques on conventional TEM tools without using low-dose imaging control interface/software. With these new methodologies or techniques, the electron-beam induced radiation damage to ultra low k IMD has been successfully minimized, and the combination of single-beam FIB milling and low-dose TEM imaging techniques can reduce structure collapse and shrinkage to almost zero.

Abnormal inline defects were caught after nitride spacer etching processes. Detailed MEBES layout checking and inline SEM inspection revealed that such defects always appeared at the boundaries in between PFETs and NFETs regions. The microstructure and chemical composition of the defects were analyzed in detail by various TEM imaging and microanalysis techniques. The results indicated that the defect possessed core-shell structure, with oxide core and nitride shell. Based on the TEM failure analysis results and manufacturing processes, we conclude that the defects originated from PR fencing due to the PR hardening during PFET and NFET LDD/Halo implantation. The oxide core was generated during oxide spacer formation using an ozone-TEOS process, which was responsible for the nitride spacer under-etch issue.

As device feature size continues to shrink, the reducing gate oxide thickness puts more stringent requirements on gate dielectric quality in terms of defect density and contamination concentration. As a result, analyzing gate oxide integrity and dielectric breakdown failures during wafer fabrication becomes more difficult. Using a traditional FA flow and methods some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. Even with some success with conventional FA the root cause was unclear. In this paper, we will propose an analysis flow for GOI failures to improve FA’s success rate. In this new proposed flow both a chemical method, Wright Etch, and SIMS analysis techniques are employed to identify root cause of the GOI failures after EFA fault isolation. In general, the shape of the defect might provide information as to the root cause of the GOI failure, whether related to PID or contamination. However, Wright Etch results are inadequate to answer the questions of whether the failure is caused by contamination or not. If there is a contaminate another technique is required to determine what the contaminant is and where it comes from. If the failure is confirmed to be due to contamination, SIMS is used to further determine the contamination source at the ppm-ppb level. In this paper, a real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made of stainless steel.

Electron beam induced radiation damage presents great challenges for the electron microscopy analysis of low k and ultra low k dielectrics due to their beam sensitive nature. In order to minimize the radiation damage, it is necessary to understand the mechanisms behind the damage. This work presents detailed studies regarding the mechanisms behind the effects of probe currents, accelerating voltage and anticharging coating layers on the radiation damage to low/ultralow K dielectrics. The results indicate that the probe current shows a stronger dependence on the size of the condenser lens aperture than the accelerating voltage. Therefore, in terms of the probe current, the condenser lens aperture plays a decisive role in affecting the radiation damage process. In order to minimize the radiation damage, SEM imaging should be conducted with not only a low accelerating voltage but also a small condenser lens aperture to reduce probe current. Based on simulation results, the effects of a coating layer and accelerating voltage are related to the interaction volume and the penetration depth of the electron beam. Pt coating can act as not only an anti-charging layer, but also an effective barrier layer for reducing electron flux that interacts with the low/ultra-low dielectrics.

Galvanic corrosion (two metal corrosion) on microchip Al bondpads may result in discolored or non-stick bondpad problem. In this paper, a galvanic corrosion case at bondpad edge will be presented. Besides galvanic corrosion (Al-Cu cell), a concept of galvanic corrosion (Al-Ti cell) is proposed, which is used to explain galvanic corrosion at bondpad edge with layers of TiN/Ti/Al metallization structure. A theoretical model of galvanic corrosion (Al-Ti cell) is proposed to explain chemically & physically failure mechanism of galvanic corrosion at bondpad edge. According to the theoretical model proposed in this paper, galvanic corrosion on microchip Al bondpads could be identified into two corrosion models: galvanic corrosion (Al-Cu cell) occurred mostly at the bondpad center and galvanic corrosion (Al-Ti cell) occurred specially at bondpad edge with TiN/Ti/Al metallization structure. In this paper, a theoretical model of galvanic corrosion (Ai-Ti cell) will be detail discussed so as to fully understand failure mechanism of galvanic corrosion the bondpad edge. Moreover possible solutions to eliminate galvanic corrosion (Al-Ti cell) are also discussed.

After wafer-die sawing process, sometimes silicon (Si) dust on microchip Al bondpads is difficult to be cleaned away by DI water, especially at pinhole/corrosive areas caused by galvanic corrosion, thus resulting in non-stick on pads (NSOP) problem in assembly process. To eliminate NSOP problem due to Si dust contamination, in this paper, we will study the mechanism of Si dust contamination and propose a concept of Si dust corrosion. A theoretical model will be introduced so as to explain Si dust contamination and corrosion problem during wafer die sawing process. Based on the mechanism proposed, Si dust contamination and corrosion is related to galvanic corrosion as OH- ions generated from galvanic corrosion will not only react with Al to cause Al corrosion, but also react with Si dust to cause Si dust corrosion. During Si dust corrosion, poly-H2SiO3 and Si-Al-O complex compounds will be formed on Al bondpads, especially at the pinholes/corrosive areas. Poly-H2SiO3 and Si-Al-O complex compounds are “gel-like” material and stick onto the surface of bondpads. It is insoluble in water and difficult to be cleaned away by DI water during or after wafer die sawing process and will cause bondpad discoloration or/and NSOP problem. Some eliminating methods of Si dust contamination and corrosion on Al bondpads during wafer die sawing process are also discussed.