Applications of Micro-Electro-Mechanical Systems (MEMS) sensors have developed rapidly in the last decade, increasing the need of Failure Analysis (FA) to characterize abnormalities and to identify failure modes of various types of MEMS devices. One of the greatest challenges is removal of the sealing cap from the MEMS device without any impact to the moveable sensing elements. A novel non-destructive technique has been successfully developed using KOH wet chemical etching followed by application of ex-situ hand sticking to deprocess the sealing cap from an accelerometer device. This new approach provides a quick and reliable way to remove the sealing cap from a MEMS device.

Contrary to traditional packages, packaging and testing of wafer-level chip scale package (WLCSP) are done before wafer dicing. The package can’t be rebuilt on a single chip; therefore, the failure analysis and debug performed by Circuit Edit (CE) on ICs with WLCSP face challenges. In addition, there are route designs on the package level of WLCSP devices, which are unique compared with traditional packages. CE is required on both chip and package level of WLCSP devices. This package technology offers the smallest possible package size; consequently, it has seen wider use lately. Developing the approaches of FIB edits on a fully-packaged WLCSP device is indeed essential. Thus, methodologies for CE and debug on WLCSP devices will be explored in this study.

Contrary to conventional Si-based device, organic thin-film transistors (OTFTs) constituting organic semiconductors are easily destroyed. Investigating failures using traditional FA techniques like electron microscopy or cross section is hard to procure. Therefore, the purpose of this paper attempts to develop approaches for failure analysis of OTFTs. We successfully demonstrate a non-destructive technique for defect inspection and localization, exactly specifying the failure of OTFT with a void existing in the organic dielectric. Application of optical beam induced resistance change (OBIRCH) in current leakage localization is shown. Non-distorted cross-section sample preparation and analysis of internal structure by electron microscopy are also developed. Moreover, the failure of OTFT induced by high driving voltage punch-through is analyzed using techniques established in the article. Particular elongation of the gate metal was found to be the failure mode.