This paper presents a study on Cu-Ag-Zn abradable seal coatings prepared by cold spraying. The micro-morphologies of the coatings were analyzed using scanning electron microscopy and electron dispersion scanning. The hardness of the coatings was analyzed. Thermal shock tests were conducted to evaluate the combination strength between the coating and the substrate. The friction and wear properties of the coatings were also tested. Two methods, annealing the coatings in vacuum and heating the feed powders in cold spraying, were tried to improve the combination strength and quality of the coating. The results showed that Cu-Ag-Zn coatings made by cold spraying with powder heating exhibited better combination strength and anti-friction properties compared to coatings annealed in vacuum and the original samples. The paper also proposed a combination mechanism for the Cu-Ag-Zn coatings.

In this paper, three productive polishing transmission electron microscopy (TEM) sample preparation methods are reported. The methods are studied to improve the efficiency and expand the application fields. Method 1 and 2 address expanding conventional polishing method application on same or similar pattern samples. Method 1 used a laser mark to identify one of the sample; and method 2 used a Pt coated glass inserted between samples or a direct deposition of Pt on one of the samples. Method 3 was developed facilitate stacking three or more samples into a single, batch process block and improved the efficiency greatly.

This paper reports optimized Transmission Electron Microscopy (TEM) sample preparation methods with Focus Ion Beam (FIB), which are used to reduce or avoid the overlapping of TEM images. Several examples of optimized cross-section sample preparation on 38nm and 45nm pitch are provided with general and novel FIB methods. And its application to plan view TEM sample preparation is also shown. The results establish that the proposed method is useful to reduce or remove pattern overlapping effects in dense structures and can produce higher quality TEM images than can be obtained using conventional top-down FIB-based TEM preparation methods.

This paper reports a novel method for site specific plan view transmission electron microscopy (TEM) sample preparation. The detailed procedure is introduced step by step. To demonstrate the practicality of this technique in failure analysis, case studies on 45nm and below technology nodes using the novel method are reported. The results showed that the method is very useful for the analysis of the specified failure location and is helpful to improve the success rate of failure analysis.

The MEMS structure has its particular character like hollow areas inside, and “floating” structures. Traditional TEM sample preparation method usually leads to distortion and dissociation defects of the floating structure. This paper introduces two innovative practical methods of TEM sample preparation using focused ion beam (FIB) for MEMS floating structure analysis. Method 1 used glass needle to lift out the separated film onto glue coated blank wafer; method 2 used in situ pick up system to lift out L- or C-shaped cut film onto TEM half-grid. And then the sample can be applied to normal TEM membrane preparation procedure.

Damage-free gate oxide is one of the important factors to ensure device performance and reliability. Special wafer accepts test structures such as a large size MOS capacitor must be laid on test line to monitor the oxide process issue and process window. However, it brings about many challenges to failure analysis engineer. To overcome the EFA and PFA limitations, fresh samples were taken from the passed wafer and the failed ones to identify the root cause of VBD failure. A novel lapping down method was used to access the capacitor structure. Two VBD failure cases were studied. In this study, poor wet clean process was defined as the cause of the silicon substrate surface damage and crystalline defect. It induced poor oxide deposition, which reduced breakdown voltage. Additionally, 12hrs BOE dip was shown to be an effective method for removing poly and oxide layers from large MOS capacitors.

Cross-sectional polishing has been widely used in the semiconductor industry. As demand for higher throughput increases, the time spent manually performing a final polish is an improper method for cross-section preparation. Etching is the major function of Precise Etching and Coating System (PECS). In this article, the focus is on Ar plasma cleaning performance on a sample after rough polishing and a sample after a short time final polishing using PECS. To evaluate performance of Ar plasma cleaning, two samples were prepared for SEM observation. X-SEM images before and after Ar plasma cleaning revealed that Ar plasma cleaning is not an effective method to correct micro scratches. The combination of final polishing and stain into one step was found to improve sample quality and throughput. PECS Ar plasma was found to be an effective sample cleaning method when compared to the time spent on final polishing.

The corrosion phenomenon was found at the edge area of bond pad under OM images after dicing saw. Experiment showed that the corrosion was related with the feed speed of dicing saw. From SEM and OM results, there were some abnormal contaminations around the corrosive area. Auger and TEM with EDX system were used to characterize the corrosive region and the related Al pad corrosion mechanism was discussed. In this paper, Cu rich and O rich layers were identified by TEM and EDX, which could be induced by galvanic cell reaction.

Electron beam assisted platinum film deposition has been found to be an effective method to protect the sample surface for both FIB and TEM analysis. In this paper, the phenomena of electron beam assisted deposition of platinum will be reviewed The results suggest that a 45 nm thick residual Pt film can effectively protects (100) silicon from damage induced by ion beam assisted Pt deposition. A carbon based organic layer under the electron beam assisted Pt has been observed. The mechanism and results on exposed oxide thickness measurements will be discussed. It is suggested that a carbon glue cap be used as a protective layer or polysilicon be deposited in line before submitting the wafer for TEM sample preparation and observation.

It has been reported that a sample prepared by ion beam milling has a sandwich structure with amorphous on two sidewalls and crystal in the middle. In this paper, the sandwich structure of such a single crystal TEM sample was studied experimentally. A novel sample and its fabrication process were reported. The sandwich structure can be observed directly in TEM with this sample. When the crystal layer in monocrystal silicon TEM sample is less than 18 nanometers, or when the sample is thinner than 64 nanometers, the sample will be observed as fully amorphous. Removal of the amorphous layer on the sample sidewalls is crucial to get TEM pictures of better quality.

The bump nodule growing in electroplating process could be large enough to induce bump to bump short even if the nodule would be weaken by re-flow process. In this work, the microstructure of PbSn eutectic bump and Au bump nodules was analyzed with FIB, SEM and EDS. In PbSn eutectic bump nodule, void defects can be observed with FIB imaging. In Au bump nodule, radiation-like grain structure around the center of Silicon-contained particle can be observed. Based on those analysis results, voids and particles are the source of bump nodule growth. The reason for bump nodule formation is that particles, voids and cathode morphology defects change the roughness of cathode surface, which induces a higher current density area and accelerate local electrocrystallization. Generally, particles, voids and cathode morphology defects are caused by poor photolithography process, tank corrosion and anode contamination such as passivation membrane. Therefore, three conclusions are proposed in this work: 1) where and when the nodules grow can be identified according to their microstructures; 2) cleaning tank and anode periodically can effectively prevent the bump nodules; 3) Qualified photo resist (PR) coating and PR opening process are essential to prevent bump nodule defects.

In this paper, the deformation mechanism of low K dielectric film under electron beams (E-beams) is discussed, and the effect of film deformation on the development of a low K dielectric film etching recipe is investigated. To provide meaningful data for process development, numerical analysis was used in the failure analysis procedure. A correction factor is formulated to calculate the change in thickness of the low K dielectric film after E-beam exposure. In addition, scanning electron microscope (SEM) settings for imaging low K dielectric films are optimized to minimize deformation.

In this paper the artifacts of additional copper signal induced by the copper grid, one of the most widely used supporting grid for focus ion beam (FIB) prepared TEM sample, is studied. Its influence on both the spot and the line scan energy dispersive spectroscopy (EDS) analyses are described. It was determined that, during line scan analysis, the strength of the copper signal varied between heavy and light elements, which could lead to inconclusive results during the EDS analysis of Cu interconnect structures. Based on the study using nickel support grid, it is concluded that the additional copper signal is a result of electrons scattered by the sample striking the Cu grid.

Accurate characterization of the nitrogen concentration and distribution in ultra thin nitrided silicon gate oxide plays the same important role as the fabrication technology itself during the development of 90nm and beyond gate oxide manufacturing process. Based on the measurement results of XPS (X-ray photoelectron spectroscopy) as reference, a correlation study was taken between XPS and AES (Auger electron spectroscopy) data in this paper. The study shows that, by optimizing the experiment conditions of AES such as beam energy, beam current and take off angle, and introducing proper corrective factor, AES can be used as a useful and reliable characterization tool during the monitoring measurement of Nitrogen concentration in ultra thin (<2nm) nitrided silicon gate oxide.

In this paper, crystal damage on TEM sample sidewalls induced by FIB milling during sample preparation was studied. A novel method was invented to prepare the sample, which facilitates the direct observation of amorphous layers on the sidewall. The ion beam acceleration voltage is the dominant factor that affects the damaged layer thickness. The measured amorphous thickness is about 23 nanometers at 30Kv and 10 nanometers at 10Kv. The damage layer thickness is constant with different beam currents over the range from 30pA to 1000pA. Amorphous layer thickness also stays constant with the sample tilt angle.

This paper examines copper-interconnect integrated circuit transmission electron microscope (TEM) sample contamination. It investigates the deterioration of the sample during ion milling and storage and introduces prevention techniques. The paper discusses copper grain agglomeration issues barrier/seed step coverage checking. The high temperature needed for epoxy solidifying was found to be harmful to sidewall coverage checking of seed. Single beam modulation using a glass dummy can efficiently prevent contamination of the area of interest in a TEM sample during ion milling. Adoption of special low-temperature cure epoxy resin can greatly reduce thermal exposure of the sample and prevent severe agglomeration of copper seed on via sidewall. TEM samples containing copper will deteriorate when stored in ordinary driers and sulphur contamination was found at the deteriorated point on the sample. Isolation of the sample from the ambient atmosphere has been verified to be very effective in protecting the TEM sample from deterioration.