The laboratory practice of employing atomic force probing (AFP) using AFP current imaging and Nanoprobe Capacitance-Voltage Spectroscopy (NCVS) at contact level (CA) for identfication of front end of line (FEOL) defects in MOSFET devices, especially for silicon on insulator applications has been extensively detailed [1,2,3]. The introduction of Nanoprobe Capacitance Voltage Spectroscopy (NCVS) on bulk silicon wafers and silicon on insulator (SOI) wafers to characterize discrete MOSFET and SOI embedded dynamic ramdom access memory devices (eDRAM) without the time consuming delayering methods of conventional scanning capacitance microscopy has also been highlighted [1,2,3,4,5,6]. Typically, this laboratory AFP characterization is employed on die fragments sampled from whole wafers following back end of the line (BEOL) metallization processing and test. The process vintage of this hardware can be as much as three months after the critical FEOL processing has occurred. This paper is intended to describe for the first time the methodology of applying AFP on whole 300mm wafers at the post CA chemical-mechanical polishing (CMP) process level to provide a real time insight into yield issues that would not be detected until subsequent BEOL metallization processing and testing. This new AFP tool incorporates enhanced features enabling both DC measurements as well as AC capacitance voltage measurements of discrete deep trench embedded DRAM (eDRAM) devices for 32nm, 28nm, and 20nm node technologies.

The technique of Nanoprobe Capacitance-Voltage Spectroscopy (NCVS) at contact level (CA) for identfication of FEOL defects in MOSFET devices, especially for silicon on insulator applications has been extensively detailed [1]. The introduction of Nanoprobe Capacitance Voltage Spectroscopy (NCVS) of discrete MOSFET and SOI embedded dynamic ramdon access memory devices (eDRAM) without the time consuming delayering methods of conventional scanning capacitance microscopy have also been highlighted [2]. This paper is intended to describe the advantages of NCVS to localize defects in specific MOSFET devices at CA level as well as to identify resistive BEOL via interconnections and FEOL defective high k metal gate structures without the attendant time consuming delayering steps employed with classical SCM methods. Localization of a FEOL defect in a discrete 32nm SOI MOSFET device in SRAM array causing a vertical pair cell failure signature will be discussed.

MOSFET devices are routinely measured at the probe pad level with conventional capacitance-voltage (CV) measurement instruments. Such measurements are done at the front end of line (FEOL) and back end of line (BEOL) process completion levels. The CV data is used to monitor the process and verify certain parametrics such as effective oxide thickness (EOT), Tox, gate drain overlap capacitance (Miller capacitance), trapped charge, diffusion/halo implant oxide leakage, doping concentration, threshold implant level and many others. This type of testing is treated at length in the classic text of Nichollian and Brews [1]. The introduction of Nanoprobe Capacitance Voltage Spectroscopy (NCVS) of discrete MOSFET devices and the method of performing scanning capacitance imaging (SCM) have been previously presented [2]. In that work, the authors used a capacitance sensor to measure the capacitance of an individual failing embedded DRAM capacitor. This paper will describe nanoprobe CV measurements of a discrete finger device from a multiple finger test structure and show comparable results obtained at the probe pad level, using an improved version of the earlier capacitance sensor. By comparing the BEOL test structure measurements with NCVS results from a single finger, we will verify and calibrate the nanoprobing technique.

Nanoprobing logic based SOI embedded DRAM cells for on-processor designs poses different challenges than probing conventional six transistor SRAM designs. This paper will describe nanoprobing logic based embedded DRAM (eDRAM) cells in 65nm SOI applications. We will also describe probe placement and measurement methodology for electrical characterization of leakage between deep trench capacitors composing those eDRAM designs. The introduction of nano CV metrology and scanning capacitance imaging for use in characterizing DRAM capacitors will also be discussed.

The emergence of multiple core, high speed microprocessors in sub 90nm node technologies present challenges for defect localization, especially in SRAM logic circuits involving Array Built In Self Test (ABIST). Voltage sensitive, temperature sensitive and frequency sensitive soft defects in these ABIST logic circuits can spell the difference between pass and failure, especially for Silicon on Insulator (SOI) designs. High density SRAM arrays with ever shrinking critical dimensions in multiple core, high speed microprocessor designs dictate an increased number of ABIST logic circuits of complex hierarchical design. Scan chain diagnostics to pinpoint the failing scan latch logic circuit following ABIST testing frequently results in ever greater uncertainty; increased number of suspect circuits related to the failure. A case study analysis successfully applied to pinpointing a voltage sensitive logic circuit defect in a 90nm SOI design is described here, followed by root cause TEM analysis.

To reconstruct discrete device threshold characteristics at tungsten contact level with atomic force probe (AFP), specific care in making drive current measurements is essential. Kelvin probing as well as the proper placement of the AFP probes themselves is an absolute requirement for insuring precise measurements. For this paper, NFET and PFET test structures employing 3 micrometer gate widths are used to simulate a sense-amp device. The results obtained using normal pad-level probing on a conventional probe station with results from an AFP nanoprober with and without Kelvin sensing are compared. These measurements are also compared with the nominal or expected design rule values. Experimental results comparing AFP Kelvin measurements at contact level on the same MOSFET test structure versus measurement obtained conventionally at pad level underscores the importance and value of AFP Kelvin measurements.

Atomic Force Probe (AFP) techniques are well suited for the electrical characterization of sub-65nm node SOI devices with multiple metal interconnect levels and low-k interlevel dielectric films. This paper discusses the use of these techniques on sub-30nm gatelength SOI MOSFETs.

As MOSFET device gate lengths shrink below the 130 nanometer node, the effects of short channel effects (SCE) and gate line edge roughness (LER) have an increasingly more pronounced affect on device performance [1-8, 10]. The 2001 International Technology Roadmap for Semiconductors (ITRS) predicts increasingly tighter critical dimensions (CD) control limits on LER from 2.7 nm in 2004 to 1.3 nm in 2010 [9,11]. As gate lengths shrink, resist etch processes emerge as the most significant contributor to LER [1-8, 11]. In addition, another contributing factor to SCE is junction implant defects. Examples of gate LER effects and junction defects in 130 nanometer node SOI SRAM MOSFET devices identified by sub-micron electrical characterization with analysis by high resolution transmission electron microscopy (TEM) are discussed.