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1-19 of 19
Michael DiBattista
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Proceedings Papers
ISTFA2024, ISTFA 2024: Conference Proceedings from the 50th International Symposium for Testing and Failure Analysis, 454-459, October 28–November 1, 2024,
Abstract
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Advanced node semiconductor reverse engineering has always demanded cutting-edge techniques to cleanly extract the key structural information from the integrated circuit (IC) design. Core circuit edit technologies such as taking a backside wafer approach, employing scanning focused ion beam (FIB) recipes, optimized chemical delivery, and endpoint technology based on ultraviolet (UV) photon spectroscopy can play an important role in success. Once delayered, the IC's structural layers can be subjected to high-resolution scanning electron microscope (SEM) imaging. A new tool has been developed that incorporates these capabilities for dedicated IC delayering. These capabilities allow for the visualization of individual layers, transistors, interconnects, and other critical elements at nanometer-scale resolution, unveiling valuable insights into the IC's design and functionality.
Journal Articles
Journal: EDFA Technical Articles
EDFA Technical Articles (2024) 26 (1): 2–50.
Published: 01 February 2024
Abstract
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The second Electronics Resurgence Initiative (ERI 2.0), sponsored by the U.S. Defense Advanced Research Project Agency (DARPA) Microsystems Technology Office (MTO), is focused on driving next generation dual use microelectronics for national security and domestic needs. The initiative focuses on creating U.S. capability for three-dimensional heterogeneous integration (3DHI) manufacturing and pursuing focused research for the manufacture of complex 3D microsystems. This guest editorial describes the outcomes from a three-day summit (Seattle, Washington, August 2023) where the initiative was launched.
Journal Articles
Journal: EDFA Technical Articles
EDFA Technical Articles (2023) 25 (4): 12–16.
Published: 01 November 2023
Abstract
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Laser-assisted copper deposition provides a key technology for analyzing complex packaging and integrated circuit challenges. Laser-based copper deposition techniques have been shown to be useful in combination with traditional FIB techniques to improve resistivity, deposition rate, and timing.
Proceedings Papers
ISTFA2022, ISTFA 2022: Conference Proceedings from the 48th International Symposium for Testing and Failure Analysis, 170-175, October 30–November 3, 2022,
Abstract
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Reproducible laser-assisted metal deposition with copper hexafluoroacetylacetonate trimethylvinylsilane Cu(hfac) (TMVS) has been demonstrated on a range of relevant semiconductor insulating material surfaces including silicon dioxide (SiO 2 ), crystalline silicon (c-Si), and organic package material such as polyimide and printed circuit board (PCB) FR- 4. A key to reliable and chemically efficient growth is a novel copper chemistry delivery methodology using direct precursor pulsing. The laser power conditions for deposition are strongly correlated to the substrate material, with increased power for the more thermally conductive samples (0.8 – 1.0 W) and significantly less for packaging materials (50 mW). The laser-assisted copper growth results and material properties are comparable to the published literature. Examples of circuit modifications using this methodology demonstrate its valuable role in the future of circuit edit.
Proceedings Papers
ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, 73-79, October 31–November 4, 2021,
Abstract
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Sub-nanometer fabrication processes and advanced packaging solutions such as 2.5D stacked silicon interconnect technology (SSIT) facilitate the production of high-performance ICs, but make physical failure analysis and debugging more difficult. For example, at 16nm, most diagnostic tools reach their limitations in terms of spatial resolution and signal sensitivity and require complex modifications and adjustments. In addition, a higher level of precision and uniformity is required for sample preparation. This paper describes a fault isolation technique that combines solid immersion lens (SIL) technology with precision die thinning. Two failure analysis case studies are presented to demonstrate the method, one a low level negative current leakage failure caused by ESD testing, the other a scan chain failure traced to the input of a delay buffer circuit. In both cases, success is attributed to the resolution and sensitivity of the SIL lens and the ability to precisely control die thickness.
Proceedings Papers
ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 357-361, November 15–19, 2020,
Abstract
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The journey to the circuit layer will be described by first discussing baseline processes of laser assisted chemical etching (LACE) steps before the focused ion beam (FIB) workflow. These LACE processes take advantage of a dual 532 nm continuous wave (CW) and pulse laser system, however limitations and overhead that is transferred over to the FIB operator will be demonstrated. Experiments show an additional third 355 nm ultraviolet (UV) pulse laser process introduction into the workflow can further reduce the remaining silicon thickness (RST) relieving FIB overhead. In addition, complex pulse laser patterning techniques will show a refinement to nonuniform produced silicon. Finally, other pulse laser patterning techniques such as polygon etch capability will allow laser etching around and in-between features to enhance circuit layer accessibility for debug operations.
Series: ASM Technical Books
Publisher: ASM International
Published: 01 November 2019
DOI: 10.31399/asm.tb.mfadr7.t91110351
EISBN: 978-1-62708-247-1
Abstract
Circuit edit has been instrumental to the development of focused ion beam (FIB) systems. FIB tools for advanced circuit edit play a major role in the validation of design and manufacture. This chapter begins with an overview of value, role, and unique capabilities of FIB circuit edit tools for first silicon debug. The etching capabilities of circuit edit FIB tools are then discussed, providing information on chemistry assisted etching in silicon oxides and low-k dielectrics. The chapter also discusses the requirements and procedures involved in edit operation: high aspect ratio milling, endpointing, and cutting copper. It then provides an introduction to FIB metal/conductor deposition and FIB dielectric deposition. Edit design rules that can facilitate prototype production from first silicon are also provided. The chapter concludes with a discussion on future trends in circuit edit technology.
Journal Articles
Journal: EDFA Technical Articles
EDFA Technical Articles (2017) 19 (4): 36–44.
Published: 01 November 2017
Abstract
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Deprocessing of ICs is often the final step for defect validation in FA cases with limited fault-isolation information. This article presents a workflow for deprocessing ICs from the backside using automated thinning and large-area plasma FIB delayering. Advantages to this approach include a reduction in manual planarization and depackaging and a higher degree of precision and repeatability.
Proceedings Papers
ISTFA2017, ISTFA 2017: Conference Proceedings from the 43rd International Symposium for Testing and Failure Analysis, 285-298, November 5–9, 2017,
Abstract
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This paper discusses the development of an extensible programmatic workflow that leverages evolving technologies in 2D/3D imaging, distributed instrument control, image processing, and automated mechanical/chemical deprocessing technology. Initial studies involve automated backside mechanical ultra-thinning of 65nm node IC processor chips in combination with SEM imaging and X-ray tomography. Areas as large as 800μm x 800μm were deprocessed using gas-assisted plasma FIB delayering. Ongoing work involves enhancing the workflow with “intelligent automation” by bridging FIB-SEM instrument control and near real-time data analysis to establish a computationally guided microscopy suite.
Proceedings Papers
ISTFA2016, ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis, 166-171, November 6–10, 2016,
Abstract
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Anticipating the end of life for IR-based failure analysis techniques, a method of global backside preparation to ultra-thin remaining silicon thickness (RST) has been developed. When the remaining silicon is reduced, some redistribution of stress is expected, possibly altering the performance (timing) of integrated circuits in addition to electron-hole pair generation. In this work, a study of the electrical invasiveness due to grinding and polishing silicon integrated circuits to ultra-thin (< 5 um global, ~ 1 um local) remaining thickness is presented.
Proceedings Papers
ISTFA2016, ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis, 391-396, November 6–10, 2016,
Abstract
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Shrinking transistor geometries present ongoing challenges for backside FIB circuit edit operations. The available space to gain access to critical signal lines has diminished to the order of hundreds of nanometers. Several previous works have shown that the diffusion of active devices can be exposed. This paper explores the effects of exposing and selectively damaging the active diffusion layer of advanced finFET process technology. STEM cross section images show that the devices are unaffected when the silicon substrate is on the order of 1-2ums. When the silicon substrate is removed to less than 100nm, the effect can be seen electrically on a set of ring oscillators.
Proceedings Papers
ISTFA2015, ISTFA 2015: Conference Proceedings from the 41st International Symposium for Testing and Failure Analysis, 460-465, November 1–5, 2015,
Abstract
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Anticipating the end of life for IR-based failure analysis techniques, a method of global backside preparation to ultra-thin remaining silicon thickness (RST) has been developed. Ultra-thin RST enables VIS light techniques such as laser voltage probing. In this work we investigate the lower RST limit due to sub-surface damage from grinding and a one-step polishing method to achieve 3 um RST (+/- 0.8 um) over 121 mm2 die (11 x 11 mm) test package as well as 5 um (+/- ) over 109.2 mm2 (8.0 x 13.7mm) active device.
Proceedings Papers
ISTFA2014, ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis, 278-283, November 9–13, 2014,
Abstract
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A key capability of focused ion beam (FIB) tools is the ability to deposit conductive materials by introducing organometallic precursors such as tungsten hexacarbonyl [W(CO)6] or (methylcyclopentadienl) trimethyl platinum [C9H17Pt]. The FIB deposited metal is often used in applications such as the modification of integrated circuits (ICs) by creating new electrical connection on the device. The electrical properties of the FIB material are of particular concern to high speed digital and radio frequency (RF) circuit designers because the resistivity of the FIB deposited metal is orders of magnitude higher in value than the near bulk resistivity value of the metals used in IC manufacturing. In this paper, we developed a correlation between the chemical composition of the FIB deposited metal and the electrical resistivity using an effective media theory (EMT) model. Analysis shows that gallium from the ion beam is the dominant contributor to lowering the resistivity of the jumper. The results of this work and model allow us to understand the role the chemical elements play in the electrical resistance of the FIB electrical jumper and to estimate the FIB metal resistance from energy dispersive spectroscopy (EDS) analysis and the geometry.
Proceedings Papers
ISTFA2014, ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis, 474-479, November 9–13, 2014,
Abstract
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The modern scanning transmission electron microscope (S/TEM) has become a key technology and is heavily utilized in advanced failure analysis (FA) labs. It is well equipped to analyze semiconductor device failures, even for the latest process technology nodes (20nm or less). However, the typical sample preparation process flow utilizes a dual beam focused ion beam (FIB) microscope for sample preparation, with the final sample end-pointing monitored using the scanning electron microscope (SEM) column. At the latest technology nodes, defect sizes can be on the order of the resolution limit for the SEM column. Passive voltage contrast (PVC) is an established FA technique for integrated circuit (IC) FA which can compensate for this resolution deficiency in some cases. In this paper, PVC is applied to end-pointing cross-sectional S/TEM samples on the structure or defect of interest to address the SEM resolution limitation.
Proceedings Papers
ISTFA2013, ISTFA 2013: Conference Proceedings from the 39th International Symposium for Testing and Failure Analysis, 111-117, November 3–7, 2013,
Abstract
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Focused ion beam (FIB) tools for backside circuit edit play a major role in the validation of integrated circuit (IC) design modifications. Process scaling is one of many significant challenges, because it reduces the accessible area to modify transistors and IC interconnects in the design. This paper examines the geometries available for FIB nanomachining, via milling/etching, and deposited metal jumpers by analyzing polygon data from computer aided design (CAD) virtual layers gathered across four process technologies, from 180nm down to 28nm. The results of this analysis demonstrate that the combination of silicon nanomachining box length and FIB via box length identifies the most challenging aspects of the FIB edit. The smallest geometries include a 300 nanometer silicon access area with a FIB milled 200 nanometer via inside it. More advanced technology nodes will require the ability to make smaller geometries without the help of integrated design features typically referred to as design for FIB/Debug.
Proceedings Papers
Preparation of Wafer Level Packaged Integrated Circuits Using Pulsed Laser Assisted Chemical Etching
ISTFA2012, ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis, 491-497, November 11–15, 2012,
Abstract
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Pulsed Laser Assisted Chemical Etching (PLACE) is an advanced method of surface preparation that etches backside silicon to ultra-thin remaining layer thickness for Focused Ion Beam (FIB) circuit edit and failure analysis of Wafer Level Packages (WLP). PLACE can achieve ultra-high purity and fine dimensional control since it is a dry process relying on pyrolytic vapor phase reactions initiated, and constrained, by a pulsed laser.
Proceedings Papers
ISTFA2008, ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis, 133-140, November 2–6, 2008,
Abstract
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We present an analysis of tungsten vias fabricated by a focused ion beam with regard to the understanding of circuit editing strategies. The growth rate of W is ~10 times faster in high aspect ratio vias than on flat surfaces, and W in vias has 4 at. % more C but only one-tenth the Ga of surface-deposited W. We propose that vias act like small Faraday cups, trapping the energy of the Ga+ ions and the reaction byproducts to enhance the growth rate of W and to increase the C to W ratio in vias compared to flat surfaces. The resistivity of W in the vias determined by a least squares fit to resistance data is 250μΩ-cm, unchanged from the resistivity of W deposited on a flat surface. The resistances of the vias fabricated in a SiO2 layer to contact an underlying Al sheet layer fit well to either of two models: 1) an effective area model that invokes resistive via sidewalls that do not participate in conduction, and 2) an contact resistance model that invokes tapered vias with a constricted W/Al contact area.
Proceedings Papers
ISTFA2008, ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis, 317-319, November 2–6, 2008,
Abstract
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Advanced semiconductor process technologies demand that patterns are milled precisely and without beam overshoot, which could damage adjacent transistors or expose neighboring interconnects. As mill box size becomes small enough and contains fewer pixels, the probability of the beam landing accurately at any given pixel for the prescribed pixel time becomes low. This has forced operators to employ higher than desired pixel times in order to preserve pattern acuity at the expense of optimized gas enhancement. In this article, the authors demonstrate the ability to machine and fill 50nm vias in advanced semiconductor process technologies. This capability is enabled directly by time of flight (ToF) operations. ToF compensation provides a significant advantage for patterning accuracy in advanced circuit edit applications. It enables FIB operators to use drastically shorter dwell times and pixel rates to enhance gas milling and deposition activities.
Proceedings Papers
ISTFA2007, ISTFA 2007: Conference Proceedings from the 33rd International Symposium for Testing and Failure Analysis, 319-326, November 4–8, 2007,
Abstract
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Circuit edit and failure analysis require tungsten deposition parameters to accomplish different goals. Circuit edit applications desire low resistivity values for rewiring, while failure analysis requires high deposition rates for capping layers. Tungsten deposition can be a well controlled process for a variety of beam parameters. For circuit edit, tungsten resistivity approaching below 150 µohm-cm and 50 μm 3 /nC is predicted. Material deposition rates of 80 μm 3 /nC can be achieved with reasonable pattern accuracy using defocus as a parameter.