A novel approach for the localization of weak points in thin transistor and capacitor oxides before electrical breakdown will be presented in this paper. The proposed approach utilizes Electron Beam Absorbed Current (EBAC) imaging based on Scanning Electron Microscopy (SEM). This technique uses the generation of additional charge carriers within the semiconductor substrate level by scanning with a focused electron beam. Over a thin transistor or capacitor oxide layer inside the interaction volume of the electron beam an increased tunnel current is visualized by EBAC and shows areas with different current intensities indicating weak points. These soft defect areas are investigated in comparison to references which were analyzed by using cross sectioning in a dual beam FIB/SEM system followed by a high resolution Transmission Electron Microscopy (TEM) investigation. The feasibility of this new technique is demonstrated on a defective transistor gate oxide test structure.

In this paper a novel approach for precise localisation of thin oxide breakdowns in transistor or capacitor structures by electron beam absorbed current (EBAC) imaging based on Scanning Electron Microscopy will be presented. The technique significantly improves sensitivity and lateral resolution of short localisation in comparison to standard techniques, e.g. Photoemission Microscopy, and provides direct defect navigation within a combined FIB/SEM system for further cross section analysis. The oxide short is minimal affected by electrical stimulation preserving its original defect structure for further physical root cause analysis. The feasibility of this new technique is demonstrated on a gate oxide (GOX) and two capacitor oxide (COX) breakdown failures.

The paper will present an approach for non-destructive localization of thermal active defects at multi chip devices combining the Lock-in Thermography and following local X-Ray inspection. In combination of both methods inner defects in inter chip connections of complex device built ups can be found in a non-destructive way before opening the device. The methods were demonstrated at defective flip chip devices with a high ohmic daisy chain with lots of chip to chip contacts. Subsequently, cross section analysis at located high ohmic contacts was performed in order to find the root cause of the failure.