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Matthew M. Mulholland
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Journal Articles
Journal: EDFA Technical Articles
EDFA Technical Articles (2023) 25 (4): 12–16.
Published: 01 November 2023
Abstract
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Laser-assisted copper deposition provides a key technology for analyzing complex packaging and integrated circuit challenges. Laser-based copper deposition techniques have been shown to be useful in combination with traditional FIB techniques to improve resistivity, deposition rate, and timing.
Proceedings Papers
ISTFA2022, ISTFA 2022: Conference Proceedings from the 48th International Symposium for Testing and Failure Analysis, 170-175, October 30–November 3, 2022,
Abstract
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Reproducible laser-assisted metal deposition with copper hexafluoroacetylacetonate trimethylvinylsilane Cu(hfac) (TMVS) has been demonstrated on a range of relevant semiconductor insulating material surfaces including silicon dioxide (SiO 2 ), crystalline silicon (c-Si), and organic package material such as polyimide and printed circuit board (PCB) FR- 4. A key to reliable and chemically efficient growth is a novel copper chemistry delivery methodology using direct precursor pulsing. The laser power conditions for deposition are strongly correlated to the substrate material, with increased power for the more thermally conductive samples (0.8 – 1.0 W) and significantly less for packaging materials (50 mW). The laser-assisted copper growth results and material properties are comparable to the published literature. Examples of circuit modifications using this methodology demonstrate its valuable role in the future of circuit edit.
Proceedings Papers
ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 357-361, November 15–19, 2020,
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The journey to the circuit layer will be described by first discussing baseline processes of laser assisted chemical etching (LACE) steps before the focused ion beam (FIB) workflow. These LACE processes take advantage of a dual 532 nm continuous wave (CW) and pulse laser system, however limitations and overhead that is transferred over to the FIB operator will be demonstrated. Experiments show an additional third 355 nm ultraviolet (UV) pulse laser process introduction into the workflow can further reduce the remaining silicon thickness (RST) relieving FIB overhead. In addition, complex pulse laser patterning techniques will show a refinement to nonuniform produced silicon. Finally, other pulse laser patterning techniques such as polygon etch capability will allow laser etching around and in-between features to enhance circuit layer accessibility for debug operations.
Proceedings Papers
ISTFA2017, ISTFA 2017: Conference Proceedings from the 43rd International Symposium for Testing and Failure Analysis, 580-584, November 5–9, 2017,
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Validation techniques on packaged integrated circuit (IC) samples positively impact time to market (TTM) by saving considerable fabrication modification turnaround time and costs. The validation techniques are typically done by working through the backside of the chip. These validation and debug techniques, such as optical probing, use the Solid Immersion Lens (SIL) for imaging and data collection. Solid Immersion Lens based near infrared (NIR) optical probing systems have been an integral function in the product life cycle enabling a fast, reliable, and low defect product to market. For the SIL configuration, the remaining silicon thickness (RST) target is specified to be 50 +/- 5um. The sample preparation tools and techniques to accomplish this have been fully developed and matured enough to provide this specification for all segment form factors. This silicon thickness is also within a sustainable thermal envelope at certain power densities during debug electrical testing and validation. As we move into the next generation of optical probing debug in the visible range, increasing resolution further, new sample preparation methods need to be developed. There are a number of different strategies and techniques to prepare the sample, while also enabling efficient heat transfer. This paper will detail some of the sample preparation techniques as a function of silicon thickness and aspect ratio. These final geometries will then be characterized thermally by investigating lateral heat distribution and junction temperature within the silicon Region of Interest (ROI). Finally, based on this sample preparation and thermal study, implications around debug techniques for optical probing will be discussed.
Proceedings Papers
ISTFA2016, ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis, 204-207, November 6–10, 2016,
Abstract
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Post silicon validation techniques specifically Focused Ion Beam (FIB) circuit editing and Failure Analysis (FA) require sample preparation on Integrated Circuits (IC). Although these preparation techniques are typically done globally across the encapsulated and silicon packaging materials, in some scenarios with tight mechanical or thermal boundary conditions, only a local approach can be attempted for the analysis. This local approach to access the underlying features, such as circuits, solder bumps, and electrical traces can be divided into two modification approaches. The back side approach is typically done for die level analysis by de-processing through encapsulated mold compound and silicon gaining access to the silicon transistor level. On the other hand, the front side approach is typically used for package level analysis by de-processing the ball grid array (BGA) and package substrate layers. Both of these local de-processing approaches can be done by using the conventional Laser Chemical Etching (LCE) platforms. The focus of this paper will be to investigate a front side modification approach to provide substrate material removal solutions. Process details and techniques will be discussed to gain access to metal signals for further failure analysis and debug. A pulse laser will be used at various processing stages to de-process IC package substrate materials.
Proceedings Papers
ISTFA2015, ISTFA 2015: Conference Proceedings from the 41st International Symposium for Testing and Failure Analysis, 274-277, November 1–5, 2015,
Abstract
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Post silicon validation techniques specifically Focused Ion Beam (FIB) circuit editing and Failure Analysis (FA) require backside sample preparation on Integrated Circuits (IC). Although these preparation techniques are typically done globally across the encapsulated and silicon packaging materials, in some scenarios with tight boundary conditions, only a local approach can be attempted for the analysis. This local approach to access the underlying features, such as circuits, solder bumps, and electrical traces will typically use conventional Laser Chemical Etching (LCE) platforms. The focus of this analysis will be to investigate and conjoin previously published techniques to this local preparation by using a combination of laser sources. A Continuous Wave (CW) and Pulse laser will be used at various processing stages to de-process IC packaging materials silicon and mold compound encapsulation.
Proceedings Papers
ISTFA2013, ISTFA 2013: Conference Proceedings from the 39th International Symposium for Testing and Failure Analysis, 490-493, November 3–7, 2013,
Abstract
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Post silicon validation techniques on Integrated Circuits (IC) specifically FIB circuit editing require backside sample preparation done by local mold compound and silicon machining. Conventional methods such as Computer Numerically Controlled (CNC) machining and chemical etching preparation platforms are commonly used. This paper will investigate a simple alternative approach to local sample preparation by using micro-abrasive blasting. This approach will display its simple natured set-up along with extremely quick process duration.
Proceedings Papers
ISTFA2011, ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis, 424-427, November 13–17, 2011,
Abstract
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Post silicon validation techniques require backside sample preparation by silicon thinning techniques. The conventional fixture to this preparation on large die packages causes silicon to crack. A new “4-point bending” fixture was developed to reduce silicon bending strain during thinning to eliminate silicon cracking. This new fixture and technique improved remaining silicon thickness uniformity as well as process time.