This paper presents a die-level sample preparation technique that uses selective etch chemistry and laser interferometry to expose the entire top metal layer surface for electrical fault isolation. It also describes a novel e-beam based probing technique called StaMPS which is used to isolate logic structure failures through SEM image contrasts. By landing SEM probe tips on exposed metal pads and controlling logic states via an applied bias, different levels of contrast are created highlighting structural failure locations. Die-level sample preparation combined with e-beam fault isolation optimizes turnaround time by delayering die in less than an hour and by locating several types of defects in a single sample.

This paper analyzes the through-put time and output of fault isolation and failure analysis (FI/FA) flows on state-of-the-art microprocessors. An average reduction in through-put time of 40% was demonstrated with a shortened FI/FA flow while still maintaining a high success rate. The direct FA/nano-probing flow which was utilized by up to around 90% of the fail cases omitted the optical fault isolation step and instead expanded the use of plasma FIB, nano-probing and electrical isolation techniques (such as diagnosis tools). The end result is shorter through-put time and higher FI/FA volume which is important in order to achieve a faster production ramp. In the paper two cases studies are presented to demonstrate the new efficient FI/FA techniques.

A laser based logic state imaging (LLSI) by activating transient voltage collapse (TVC) circuits of SRAM blocks is demonstrated. In order to induce a voltage modulation on a power rail, significant numbers of TVC units are activated. The image quality of LLSI strongly depends on a number of activated TVC circuits. From this experiment, it is concluded that an additional circuit or experimental setup is not necessary for LLSI.

Resolution of optical fault isolation (FI) and nanoprobing tools needs to keep pace with the device downscaling to be effective for semiconductor process development. In this paper we present and discuss state-of-the-art FI and nanoprobing techniques evaluated on Intel test-chips fabricated on next generation process technology. Promising results were obtained but further improvements are necessary for the 7nm node and beyond.

A novel fault isolation technique, electron beam induced resistance change (EBIRCh), allows for the direct stimulation and localization of eBeam current sensitive defects with resolution of approximately 100nm square, continuing a history of beam based failure isolation methods. EBIRCh has been shown to work over a range of defects, significantly decreasing the time required for isolation of shorts through straightforward high resolution imagery, allowing for explicit visual defect isolation with a linear resolution of approximately 10nm. This paper discusses the operational setups for the source and amplifier while performing an EBIRCh scan, describes the processes involved in the Intel test vehicle that was used to test EBIRCh, and provides information on two independent functional theories for EBIRCh that operate in conjunction to a greater or lesser extent depending on the defect type. EBIRCh is expected to improve through-put and resolution on various defect types compared to conventional fault isolation techniques.

A novel method for obtaining diffraction limited high resolution images, and increased signal to noise ratio (SnR), for imaging and probing silicon based complementary metal oxide semiconductor field effect transistor (CMOS, and MOSFET) integrated circuits (IC), is presented. The improved imaging is based on the sub wavelength features’ asymmetric layout, which is dictated by the lithography design rules constrain in CMOS IC and their interactions with polarized light. This asymmetry in layout and the inherent stress engineering on the CMOS IC, produce both dichroism and birefringence in silicon (Si). An elegant design enabled us to obtain two images with orthogonal polarization detection to take advantages of the dichroism and birefringence in Si based CMOS IC. Differential Polarization Image (DPI) is obtained by subtracting the two orthogonal polarization resolved images. On infrared emission microscopes (IREM), DPI in optical imaging mode and DPI plus probing [DPIP] in emission mode, showed 2X or more in terms of optical resolution (imaging mode) and 2X or more SnR (emission-probing mode) improvements. Striking images in probing mode, revealing previously “invisible” emission, were demonstrated.