In this paper, we present methods for targeted silicon thinning by contour milling to overcome challenges associated with thinning large devices to under 5 µm remaining silicon thickness. Implementation of these techniques are expected to improve the yield of ultra-thin sample preparation and thermal stability of the device through electrical failure analysis for subsequent physical failure analysis. Using a computer numerical controlled milling system, the natural device bow is exploited to thin a specified area of interest by stage tilting before 2D milling. To target a larger area of interests, contour maps are rigged to thin an area preferentially while remaining compatible with existing workflows. Electrical testing have found improved thermal stability of the locally thinned samples over globally thinned samples.

Deprocessing and probing are two quintessential steps in the physical failure analysis (PFA) and competitive analysis of integrated circuits (ICs). Typically, these steps are accomplished using multiple tools, which include polishers, electron microscopes, and probers. To combat the aggressive back-end-of-line (BEOL) scaling which has significantly decreased the controllability of manual polishing, gas-assisted Xe plasma FIB has been employed to achieve large area uniform delayering. Combined with an in-situ probing capability within the plasma FIB, the iterative process of juggling between tools is streamlined into a seamless process. In this paper, the successful integration of Prober Shuttle and plasma FIB to isolate and visualize real defects on sub-20 nm microprocessor chips are presented.

High resolution laser imaging, using high numerical aperture (NA) solid immersion lens (SIL) for backside fault isolation imposes stringent sample preparation requirements; as a result of the short focal length of SIL, a die must be thinned to a targeted thickness with less than a ±5 μm silicon thickness variation across the entire die. Flip chip packaged dice suffer from warpage due to various package sizes and substrate thicknesses. Such broad spectrums of part geometries pose a great challenge to meet such silicon planarity requirements. As relaxation of the packaged silicon during polishing causes the warpage profile to change dynamically and unpredictably throughout the thinning process, it has become an added challenge to meet the stringent sample preparation requirements. To overcome the stochastic nature of this problem, a two-step polishing recipe consisting of computer numerical control (CNC) mechanical milling and polishing processes has been developed to achieve sufficient silicon thickness uniformity to enable SIL imaging across an entire silicon chip as large as approximately 20 mm x 15 mm.

Space-domain reflectometry (SDR) utilizing scanning superconducting quantum interference device (SQUID) microscopy is a newly developed non-destructive failure analysis (FA) technique for open fault isolation. Unlike the conventional open fault isolation method, time-domain reflectometry (TDR), scanning SQUID SDR provides a truly two-dimensional physical image of device under test with spatial resolution down to 30 μm [1]. In this paper, the SQUID SDR technique is used to isolate dead open faults in flip-chip devices. The experimental results demonstrate the capability of SDR in open fault detection

An enhanced back-side deprocessing recipe has been established with an additional heat step compared to previous methods. This enhanced recipe reduces overall deprocessing time by 70%. The edges with higher silicon thickness can be polished simultaneously. This recipe has proved repeatable and successful across different technology nodes and die sizes.