In this work, we present two case studies on the utilization of advanced nanoprobing on 20nm logic devices at contact layer to identify the root cause of scan logic failures. In both cases, conventional failure analysis followed by inspection of passive voltage contrast (PVC) failed to identify any abnormality in the devices. Technology advancement makes identifying failure mechanisms increasingly more challenging using conventional methods of physical failure analysis (PFA). Almost all PFA cases for 20nm technology node devices and beyond require Transmission Electron Microscopy (TEM) analysis. Before TEM analysis can be performed, fault isolation is required to correctly determine the precise failing location. Isolated transistor probing was performed on the suspected logic NMOS and PMOS transistors to identify the failing transistors for TEM analysis. In this paper, nanoprobing was used to isolate the failing transistor of a logic cell. Nanoprobing revealed anomalies between the drain and bulk junction which was found to be due to contact gouging of different severities.

With technology scaling of semiconductor devices and further growth of the integrated circuit (IC) design and function complexity, it is necessary to increase the number of transistors in IC’s chip, layer stacks, and process steps. The last few metal layers of Back End Of Line (BEOL) are usually very thick metal lines (>4μm thickness) and protected with hard Silicon Dioxide (SiO2) material that is formed from (TetraEthyl OrthoSilicate) TEOS as Inter-Metal Dielectric (IMD). In order to perform physical failure analysis (PFA) on the logic or memory, the top thick metal layers must be removed. It is time-consuming to deprocess those thick metal and IMD layers using conventional PFA workflows. In this paper, the Fast Laser Deprocessing Technique (FLDT) is proposed to remove the BEOL thick and stubborn metal layers for memory PFA. The proposed FLDT is a cost-effective and quick way to deprocess a sample for defect identification in PFA.

With continuous scaling of CMOS device dimensions, sample preparation for Transmission Electron Microscope (TEM) analysis becomes increasingly important and challenging as the required sample thickness is less than several tens of nanometers. This paper studies the protection materials for FIB milling to increase the success rate of ex-situ ‘lift-out’ TEM sample preparation on 14nm Fin-Field Effect Transistor (FinFET).

With further technology scaling, it becomes increasingly challenging for conventional methods of failure analysis (FA) to identify the cause of a failure. In this work, we present three case studies on the utilization of advanced nanoprobing for SRAM circuit analysis and fault identification on 20 nm technology node SRAM single bit devices. In the first 2 case studies, conventional failure analysis by passive voltage contrast (PVC) failed to identify any abnormality in the known failed bit. In the third case study, an abnormally bright PVC was observed by PVC inspection. In all three case studies, static noise margin of the SRAM bits during hold and read operations were performed to understand the circuit behavior of the failed bit cell. Next, nanoprobing on the individual transistors were performed to determine the failing transistor within the bit and the possible cause of the failure. TEM analysis was performed to identify and verify the failure mechanism.

Conductive-Atomic Force Microscopy (C-AFM) is a popular failure analysis method used for localization of failures in Static Random Access Memory (SRAM) devices [1-4]. The SRAM structure has a highly repetitive pattern where any abnormality in a failed cell compared to neighboring cells could be easily identified from its current image [5-7]. Unlike topographical imaging, the C-AFM requires the probe tip to be coated with a conductive layer in order to pick up the electrical signals from the device under test. The coating needs to be sufficiently thick as it would wear off after a certain amount of physical scanning. This additional coating on the AFM tip is essential but poses a limit to the tip radius curvature. The commercially available tip radius is approximately 35nm (DDESP-10 from Bruker) and the dimension is too large for imaging of 20nm technology device. However, the limitation could be alleviated by subjecting the sample surface to treatment prior to C-AFM imaging. The aim of this surface treatment is to ensure C-AFM tip maintains sufficient scanning contact with the tiny conductive (tungsten) structure of the sample in order to achieve distinct current image. The surface treatment is done by creating a receding Inter-Layer Dielectric (ILD) from its neighboring tungsten contact. The creation of the receding depth could be achieved by either wet etching or dry etching (Reactive Ion Etching, RIE). In this work, the surface treatments by these two methods have been investigated and the recipe is optimized to obtain a clear current image. The optimized recipe is then applied on actual failure analysis where three cases are studied.

With the scaling of semiconductor devices to nanometer range, ensuring surface uniformity over a large area while performing top down physical delayering has become a greater challenge. In this paper, the application of laser deprocessing technique (LDT) to achieve better surface uniformity as well as for fast deprocessing of sample for defect identification in nanoscale devices are discussed. The proposed laser deprocess technique is a cost-effective and quick way to deprocess sample for defect identification and Transmission Electron Microscopy (TEM) analysis.

Top-down, layer-by-layer de-layering inspection with a mechanical polisher and serial cross-sectional Focused Ion Beam (XFIB) slicing are two common approaches for physical failure analysis (PFA). This paper uses XFIB to perform top-down, layer-by-layer de-layering followed by Scanning Electron Microscope (SEM) inspection. The advantage of the FIB-SEM de-layering technique over mechanical de-layering is better control of the de-layering process. Combining the precise milling capability of the FIB with the real-time imaging capability of the SEM enables the operator to observe the de-layering as it progresses, minimizing the likelihood of removing either too much or too little material. Furthermore, real time SEM view during top-down XFIB de-layering is able to provide a better understanding of how the defects are formed and these findings could then be feedback to the production line for process improvement.

SEM-based nanoprobing has proven vital in identifying nonvisual failures through electrical characterization in current FA metrology for fault identification. With eight probes used concurrently, the system could have the ability to obtain other important information such as cell stability as well as the static noise margin (SNM). In this work, the cell stability and SNM at different biasing conditions at low electron beam energy (500eV) of a sub-30 nm technology node SRAM device have been characterized. Bit cell stability, static noise margin test as well as leakage study between two adjacent floating wordines were performed on the SRAM samples. Results show that no significant degradation has been introduced during the data acquisition and imaging processes in the SEM. Good resolution imaging with passive voltage contrast can be achieved with low electron voltage (500eV) throughout the nanoprobing process.

With the scaling down of semiconductor devices to nanometer range, fault isolation and physical failure analysis (PFA) have become more challenging. In this paper, different types of fault isolation techniques to identify gross short failures in nanoscale devices are discussed. The proposed cut/deprocess and microprobe/bench technique is an economical and simple way of identifying low resistance gross short failures.