Backside circuit edit (CE) remains a crucial failure analysis (FA) capability, enabling design modifications on advanced integrated circuits. [1-9] A key requirement of this activity is to approach the active transistor layer of the silicon through the removal of the silicon substrate without exposing or damaging critical transistor features. Several methods have been previously developed to enable or assist with the process with either global or locally targeted techniques for thinning the silicon substrate. These methods employ mechanical methods, laser based techniques (continuous or pulsed), or chemical assisted focused ion beam (FIB) etching to accomplish the thinning. Each of these methods presents different strengths and weaknesses, from their reliability to complexity, but very few techniques provide a precise and accurate quantitative measure of the remaining silicon thickness (RST). Here, we will discuss the use of a FIB with XeF2 for backside Si removal, and the development of an in-situ, accurate measurement of RST.

By combining transmission electron microscopy (TEM) [1] with scanning capacitance microscopy (SCM) [2], it is possible to enhance our understanding of device failures. At Sandia, these complementary techniques have been utilized for failure analysis in new product development, process validation, and yield enhancement, providing unique information that cannot be obtained with other analytical tools. We have previously used these instruments to identify the root causes of several yield-limiting defects in CMOS device product lines [3]. In this paper, we describe in detail the use of these techniques to identify electrically active silicon dislocations in failed SRAMs and to study the underlying leakage mechanisms associated with these defects.