Characterizing and fault localizing sub 0.25μm six level copper BEOL microprocessor RISC designs operating above 450 MHz clock speeds pose significant challenges in functional defect localization and identification. The flip chip designs of these microprocessors with high numbers of I/O outputs can involve backside and frontside fault localization techniques such as emission microscopy, OBIC (Optical Beam Induced Current) using I.R. laser scanning microscopy, LIVA (Light Induced Voltage Alteration) [1,2], and PICA (Picosecond Imaging Circuit Analysis)[3,4], to identify the source of functional failures. Refined backside thinning techniques have been applied to optimize I.R. laser scanning microscopy and PICA localization of functional failures. In addition, products using highly structured test methods such as LSSD(Level Sensitive Scan Design) lend themselves to a highly software diagnosable category [5,6]. Such software diagnostics (LSSD diagnostics) when combined with image based fault localization has proven highly effective in pinpointing defects causing functional failures. Examples of electrical and physical characterization of functional logic failures in the six levels electroplated copper BEOL microprocessors will be described. In addition, the electrical characterization of submicron sized SRAM transistor devices using FIB (Focused Ion Beam Microscopy)deposited probe pads [7] will be detailed along with SEM and TEM micrographs of defects identified in this manner.