This paper describes a backside approach methodology for sample preparation, fault localization and physical defect analysis on p-GaN power HEMT electrically stressed in DC voltage surge and AC switching mode. The paper will show that preparation must be adapted according to the defect position (metallurgy, dielectric layers, epitaxy, etc.) which depends on the type of stress applied. In our life-operation mode amplified electrical stress reliability study, the failure analysis will help us to reveal the weakest parts of the transistor design in relation to the type of applied stress. The failure analysis presented in this paper is composed of electrical characterization, defect localization with PEM and LIT, FIB Slice&View, TEM analysis and frontside conductive AFM after a deep HF.

We report on a new non-destructive electrical fault isolation (EFI) technique to localize interconnection failures in through-silicon via (TSV) structures for three-dimensional (3-D) integration. The scanning optical microscopy (SOM) technique is based on light-induced capacitance alteration (LICA) and uses localized photon probing of TSV interconnect capacitance to localize interruptions of electrical connectivity. The technique is applicable to passivated devices and allows rapid, efficient, and non-destructive fault isolation at wafer level. We describe the physics behind signal generation of the technique and demonstrate the TSV photocapacitance effect. We further demonstrate the LICA technique on open failed TSV daisy chain structures and confirm our results with microprobing and voltage contrast measurements in a scanning electron microscope (SEM).