In this paper, we discuss a set of techniques and analysis methodologies for the reverse engineering and functionality extraction of complex mixed-signal ICs with a special focus for security applications. Front and back side reflected light pattern images at different magnifications are used to identify circuit blocks. Time-integrated and time-resolved photon emission data is used to identify gate logic states, sequences of events, and specific functional activity. Backscattered electron and scanning transmission electron images mosaics are used to reverse engineer individual gates and observe local interconnects. Thermal imaging is used to aid in the functional block identification and analog gates analysis. Different advanced methodologies for tool automation, focusing, mapping, and image processing are also discussed in the context of our proposed electro-optical tester based technique.

Transmission Electron Microscopy (TEM) and scanning TEM (STEM) is widely used to acquire ultra high resolution images in different research areas. For some applications, a single TEM/STEM image does not provide enough information for analysis. One example in VLSI circuit failure analysis is the tracking of long interconnection. The capability of creating a large map of high resolution images may enable significant progress in some tasks. However, stitching TEM/STEM images in semiconductor applications is difficult and existing tools are unable to provide usable stitching results for analysis. In this paper, a novel fully automated method for stitching TEM/STEM image mosaics is proposed. The proposed method allows one to reach a global optimal configuration of each image tile so that both missing and false-positive correspondences can be tolerated. The experiment results presented in this paper show that the proposed method is robust and performs well in very challenging situations.

In this paper, we propose a new methodology and test system to enable the early detection and precise localization of Time-Dependent-Dielectric-Breakdown (TDDB) occurrence in Back-End-of-Line (BEOL) interconnection. The methodology is implemented as a novel Integrated Reliability Test System (IRTS). In particular, through our methodology and test system, we can easily synchronize electrical measurements and emission microscopy images to gather more accurate information and thereby gain insight into the nature of the defects and their relationship to chip manufacturing steps and materials, so that we can ultimately better engineer these steps for higher reliable systems. The details of our IRTS will be presented along with a case study and preliminary analysis results.