During package qualification, a 5-die-stacked chip scale package was being marginally triggered on high stand-by current collectively known as Power ICCS failure. Affected lots are subjected to 3x reflow at 240°C. Post reflow failures include blown_up, high standby current in Vcc pin (ISBLO), and high standby current in Vccq pin (ISBLOQ). Backside chip-outs are observed on Die 1 and Die 3 of the three failures. Electrical validation showed that only Die 3 is failing. Corner crack on Die 3 is common to the blown_up and ISBLO failing units while crack on Die 3 backside is observed to propagate toward the active area on ISBLOQ failing units. Fracture analysis results show that the crack of the three failures all originated from die backside chip-out. Thermo-mechanical model of the package shows that, by design, Die 3 generates the highest stress concentration. Results show that if chip-outs are present on the area of the die with the highest stress concentration and the unit is subjected to reflow temperature of 240°C, die crack will propagate from the chip-out. This paper presents the unique failure mechanism observed on a 5-die-stacked chip scale package and the corrective actions applied to solve the issue.

The increasing demand for high end electronic devices incorporating multiple functions in a small form factor leads to the widespread use of Stacked Chip Scale Packaging (SCSP) in the semiconductor industry. Multiple die stacking in various combinations have been achieved. However, new failure mechanisms are being observed due to new package stress characteristics. This paper will present a unique failure mechanism observed on the bottom die of a multiple die stack package. A detailed discussion of the failure mechanism showing the interaction between the presence of a high die attach adhesive fillet and the die singulation damage initiating a thin film delamination from the die edge towards the active circuit area causing electrical failures will be presented.