It has been a challenge to perform failure analysis for miniaturization of process node technology in high-speed transceiver. Failure analysis plays an important role in root cause analysis to enable R&D, product quality & reliabily improvement. This paper demonstrated an effective FA approach on a real case with ADPLL functional failure within a high-Speed transceiver in complex sub-nano FPGA. This successful case is achieved by incorporating Analog Probe (APROBE), Infrared Emission Microscopy (IREM), extensive layout study, delayering, Nanoprobing and Scanning Electron Microscopy (SEM) for defect localization.