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Proceedings Papers
ISTFA2024, ISTFA 2024: Tutorial Presentations from the 50th International Symposium for Testing and Failure Analysis, h1-h68, October 28–November 1, 2024,
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Presentation slides for the ISTFA 2024 Tutorial session “A Practical Tutorial on ATE-Based Electrical Fault Isolation of Digital SoCs Using Photon Emission and Laser Voltage Imaging/Probing (2024 Update).”
Proceedings Papers
ISTFA2024, ISTFA 2024: Conference Proceedings from the 50th International Symposium for Testing and Failure Analysis, 125-134, October 28–November 1, 2024,
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As System-on-a-Chip (SoC) continues to increase in complexity, multiple functionalities are being integrated into one integrated circuit (IC). This requires optimization of Design-for-Testability (DFT) strategies to minimize test time while still ensuring full test coverage of the entire chip. It has led to the widespread adoption of Tessent Streaming Scan Network (SSN) architecture on advanced technology nodes. Unlike traditional scan architectures that send data directly to the scan chains, SSN breaks down the data into packets and optimizes the delivery of these packets to allow efficient, concurrent testing of any number of cores. However, SSN presents a challenge for failure analysis, as it becomes extremely difficult to directly modify the SSN patterns on the fly to create a stimulus that will be used for many of the electrical fault isolation (EFI) techniques such as Laser Voltage Imaging (LVI) and Probing (LVP), Dynamic Laser Stimulation (DLS) and Photon Emissions Analysis (PEM). Key challenges include the inability to loop test patterns, run periodic sequences and no visibility of the scan control and clock signals, since these signals are internally generated by the SSH during retargeting. This paper introduces a new Tessent DFT enhancement developed by Siemens called the “LVX mode”. It is the first feature designed to enable Failure Analysis within a DFT tool, utilizing specific DFT hardware for implementation. In addition, another DFT feature which enables writing special pattern annotations that will indicate the start and end of a capture window and the location of all the capture pulses within that window for a particular pattern will also be presented, together with a methodology that will enable static Photon Emissions on SSN patterns. Since on-the-fly modification of the patterns is not possible in SSN, this paper will present two methods that would allow for a more effective and efficient DLS looping. Lastly, the paper will showcase multiple use cases that demonstrate the effectiveness of these identified DFT enhancements for FA.
Proceedings Papers
ISTFA2023, ISTFA 2023: Tutorial Presentations from the 49th International Symposium for Testing and Failure Analysis, g1-g70, November 12–16, 2023,
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Presentation slides for the ISTFA 2023 Tutorial session “A Practical Tutorial on ATE-Based Electrical Fault Isolation of Digital SoCs Using Photon Emission and Laser Voltage Imaging/Probing.”
Journal Articles
Journal: EDFA Technical Articles
EDFA Technical Articles (2023) 25 (4): 57–58.
Published: 01 November 2023
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The EDFAS Die-Level Roadmap Committee was formed to identify forthcoming challenges related to electrical fault isolation within the next five years and collaborate with various stakeholders, including industry, academia, and tool vendors, to devise practical solutions. To that end, the team has pinpointed five critical areas of focus: (1) laser-based, photon emission, and thermal; (2) 2D/2.5D/3D packaging; (3) product yield, test, and diagnostics; (4) general (leading edge technologies); and (5) system level, analog/RF, and digital functional.
Series: ASM Technical Books
Publisher: ASM International
Published: 01 November 2023
DOI: 10.31399/asm.tb.edfatr.t56090021
EISBN: 978-1-62708-462-8
Abstract
Recent trends in electronic packaging, including the growing use of 3D designs and heterogeneous integration, are greatly adding to the complexity of isolating faults in semiconductor products. This chapter reviews the latest IC packaging and integration solutions and assesses the readiness level of fault isolation tools and techniques. It examines the capabilities, limitations, and optimization potential of x-ray tomography and magnetic field imaging, describes various approaches for optical fault isolation, and compares and contrasts pre-OFI sample preparation methods. The chapter also explains how time-domain and electro-optical terahertz pulse reflectometry are used to find shorts and opens in ICs and how challenges related to heterogenous integration may be met through design for testability (DFT) and built-in self-test (BIST) accommodations and the use of passive interposers.
Proceedings Papers
ISTFA2022, ISTFA 2022: Conference Proceedings from the 48th International Symposium for Testing and Failure Analysis, 115-119, October 30–November 3, 2022,
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Hard functional and logic failures which are insensitive to temperature, voltage, or frequency have become increasingly difficult to debug in advanced technology nodes, especially when Photon Emission (PEM) analysis could not provide any leads and Dynamic Laser Stimulation (DLS) could not be used due to the nature of the failure (no pass/fail margin). Laser Voltage Imaging (LVI), which is an extension of the Laser Voltage Probing (LVP) technique, provides a visual map of active components that are toggling at a certain frequency. This technique is widely employed in scan chain debug due to its simplicity, efficiency, and accuracy. However, most of LVI applications in literature reviews only involve scan chain fault isolation. This paper will present alternative applications for LVI, apart from scan chain debug. One specific application is the debug of a broken signal path by sending a periodic signal as a stimulus to a GPIO pad and tracing the LVI signal through the path by frequency mapping. In this paper, the concept and methodology behind this fault isolation approach will be discussed in full detail. Furthermore, three case studies of different types of hard failures with different applications of LVI will also be presented: an IO functional failure, an ATPG (Automatic test pattern generation) SAF (Stuck At Fault) failure and a BSDL(Boundary scan description language) input interconnect failure, to illustrate how LVI could be deployed in fault isolation for those functional and logic hard failures.
Proceedings Papers
ISTFA2022, ISTFA 2022: Conference Proceedings from the 48th International Symposium for Testing and Failure Analysis, 352-354, October 30–November 3, 2022,
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Photon Emission Microscopy (PEM) analysis is one of the most common used FA techniques to identify the root cause of failures within ATPG scan logic due to its ease of setup and less invasive nature. While conducting photon emissions, the device is made to operate in the fail mode by running a production test vector to look for anomalous emissions or hot spots that could narrow down the area of interest (AOI) for subsequent Physical Failure Analysis (PFA). However, if there is no clue from emission analysis in the case of a hard failure with no sensitivity to voltage, frequency, or temperature, FA debug will be challenging. This paper shows how PEM analysis success may be further improved through logic state circuit study using a DFT ATPG diagnostic platform. Logic state truth table and its relative test pattern will be built based on the diagnostic data using in-house scripts, and the test program can then be changed to the required condition of the circuitry. With the altered logic state, new emission data can be collected, which could potentially reveal new clues to the investigation.
Proceedings Papers
ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, 369-376, October 31–November 4, 2021,
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This paper presents a user-defined fault model (UDFM) that accounts for silicon behaviors that cannot be explained using traditional stuck-at and transition delay fault models. The new model targets cell-internal faults but does not require time-intensive SPICE simulations because it operates at the logic level. As added benefit, error logs collected using UDFM patterns (instead of traditional models) can be used to generate diagnostic callouts with improved resolution. A workflow that effectively achieves this is presented in the paper along with three case studies that demonstrate the usefulness of the proposed method.
Proceedings Papers
ISTFA2016, ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis, 574-579, November 6–10, 2016,
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Defect localization has become more complicated in the FinFET era. As with planar devices, it is still generally possible to electrically isolate a failure down to a single transistor. However, the complexity of certain FinFET devices can lead to ambiguity as to the exact physical location of the defect. The default technique for isolating the defect location for this type of device is to start with a plan view S/TEM lamellae. Once the defect is located in plan view, the lamellae can be converted to cross-section (if necessary) for further characterization. However, if the defect is not detectable in plan view S/TEM analysis, an alternative approach is to examine the device in cross-section along either the x- or y- axis. Once the defect is located in the initial cross-sectional lamellae, it can be converted to the orthogonal axis if the initial cross-sectional lamellae did not provide adequate information for characterization. However, in converting a cross-sectional lamellae to the orthogonal axis, the initial lamellae must be exceedingly thin due to the dimensions of devices on 1x nm FinFET technologies, else other structures on the sample can obscure the view in the S/TEM. This can lead to structural integrity (warping) issues for the converted lamellae. In this paper, a novel solution to the warping issue is presented.