Failure Analysts are often required to work on a vast array of part types. These integrated circuits (IC) can have wide ranging functions and applications. Also, the ICs can be offered in a multitude of package types. All these factors compound the challenges faced by the Failure Analysts. This paper provides a brief snapshot of one approach adopted by the ON Semiconductor Product Analysis Labs to prepare in advance for the products that offer significant challenges in terms of electrical bench testing and fault localization. The approach demonstrates how the prospects of success of a given failure analysis (FA) case can be improved by making available smart solutions that cut down on the effort required for bench testing, defect localization and failure verification activities. This in turn can contribute to cycle time reduction and improve overall efficiency of the FA process.

A novel approach for solid immersion lens (SIL) assisted imaging and backside analysis of chip-on-board devices is presented. The procedure relies on complete die extraction from its original package, and repackage into a FA-friendly Plastic Quad-Flat Package (PQFP) chip carrier with inverted mold configuration, which enables access to the backside of the die through grinding/polishing or other methods. This procedure also relies on complementing use of device-specific DUT boards with generic arrangement of I/O, ground and power domains, coupled with a bench-test board equipped with the same pin-out configuration and a custom carrier built specifically for these DUT boards. This generic approach broadens the use of this solution to an entire family of devices and offers a balance of test capability leading to fault localization success and cost control.