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L. Tierney
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Proceedings Papers
ISTFA2024, ISTFA 2024: Conference Proceedings from the 50th International Symposium for Testing and Failure Analysis, 79-81, October 28–November 1, 2024,
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In the ever-increasing complexity of today’s state-of-the-art semiconductor structures, it is desirable to seek any advantage in the fault isolation and analysis paradigm to improve time to data. This paper discusses one such improvement where it is shown to be possible to target silicon (Si) devices, their metal contacts, or any other location in the wafer stack in a SRAM test structure from metal level 7 (M7) for transmission electron microscopy (TEM) sample fabrication using a modified sample geometry, focused ion beam (FIB) software targeting tools, and planning for failure analysis at the mask design stage. Electron beam inspection data was used to drive back to the location of interest in this example. The subsequent analysis shows a silicon and oxygen rich material creating an open contact defect signature.
Proceedings Papers
ISTFA2022, ISTFA 2022: Conference Proceedings from the 48th International Symposium for Testing and Failure Analysis, 74-77, October 30–November 3, 2022,
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Non-planar semiconductor devices, such as vertical fin-based field-effect transistor (FinFET) devices have been developed that include multiple vertical fins serving as conducting channel regions to enable larger effective conduction width in a small layout area. However, as circuits are scaled to smaller dimensions, it has become increasingly difficult to improve the performance of FinFET devices. Stacked nanosheet FETs have been developed to further enable larger effective conduction width in a given small layout area while enabling gate length scaling. Nanosheet (NS) FET devices have attracted attention as a candidate to replace FinFET technology at the 5 nm technology node and beyond due to their excellent electrostatics and short channel control. The use of silicon-germanium for the channel material has been explored as a major technology element for FinFET CMOS technology, and the performance benefits of Si-Ge channel over silicon channel have been demonstrated. Compared with conventional FinFET, stacked gate-all-around (GAA) NS CMOS shows higher electron mobility for nFET but lower hole mobility for pFET due to its unique device architecture and carrier transport direction. To improve pFET performance, SiGe NS is proposed as the pFET channel material. However, introducing and maintaining strain in the SiGe GAA NS channel is challenging but important for improving carrier transport. It is critical to understand the strain distribution in the advanced 3D nanosheet FET structures. This paper describes the use of advanced transmission electron microscopy (TEM) techniques to investigate the strain distribution in strained SiGe channel NS pFET through Si channel trimming and selective Si1-xGex epitaxial growth. A stacked GAA NS pFET was fabricated from compressively strained Si1-xGex channel with good crystallinity and high uniaxial compressive stress of ~1 GPa. From lattice deformation maps with a nanometer spatial resolution obtained by TEM techniques, the authors demonstrate that nano-beam precession electron diffraction techniques can be used to investigate the local strain distribution of the stacked GAA NS pFET devices with high precision, and thus help to optimize the integration process and strain engineering for pFET device performance enhancement for the next generation of CMOS logic in GAA NS technology.
Proceedings Papers
ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, 34-39, October 31–November 4, 2021,
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There are several variants of artificial intelligence (AI) hardware structures that are under study by the semiconductor industry for potential use in complementary metal–oxide–semiconductor (CMOS) designs. This paper discusses some of the failure analysis challenges that have appeared in discrete test structures and test arrays developed as part of an exploratory phase-change memory (PCM) program at IBM's Albany AI Hardware Research Center.
Proceedings Papers
ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, 206-210, October 31–November 4, 2021,
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In this work, we investigate mushroom type phase-change material (PCM) memory cells based on Ge 2 Sb 2 Te 5 . We use low-angle annular dark field (LAADF) STEM imaging and energy dispersive X-ray spectroscopy (EDX) to study changes in microstructure and elemental distributions in the PCM cells before and after SET and RESET conditions. We describe the microscope settings required to reveal the amorphous dome in the RESET state and present an application example involving the failure analysis of a PCM test array made with devices fabricated at IBM’s Albany AI Hardware Research Center.
Proceedings Papers
ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 198-201, November 15–19, 2020,
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Power consumption of conventional CMOS semiconductor architectures has grown to the point where novel structures need to be introduced to mitigate the power load within the chip. The introduction of the specialized artificial intelligence devices goes hand in hand with the inception of novel materials and processes into conventional semiconductor fabrication, which drives the need for expanding the host of failure analysis techniques and diagnostic capabilities. This paper describes a case study of elemental transmission electron microscopy tomography on an exploratory phase change memory test structure and comments upon some technique observations: advantages and disadvantages.