System failure due to a progressive defect in memory cell-array of DRAM was studied with automated test equipment. In order to find out relationship correctable single-bit fault and system failure, memory cells with single-bit fault by a cross-defect were selected. After high voltage and temperature stress, a soft cross-defect was changed into a hard cross-defect. Consequentially, invalid operation by a degraded cross-defect causes array-failure. Based on the failure analysis, methods to prevent array-failure are proposed, and applied to DRAM successfully.

As microelectronic feature sizes are scaled down, the characteristics and distribution of DRAM data retention time and write recovery time are getting worse. This degradation is due to the increases in the leakage current and resistance of the cell node and the decrease of cell capacitance in DRAM devices. As the physical distance between storage nodes decreases, node potential is increasingly affected by small potential changes in adjacent storage nodes. In this paper, we will show that the one of the most dominant contributors to failure is the adjacent storage node level, and we will demonstrate how node level affects write time delay. The effect of the adjacent storage node level can be correlated with a change in threshold voltage, much like the MOSFET body effect. We define this phenomenon as the lateral body effect, and propose a model for adjacent potential effect using the Buried Cell Array Transistor (BCAT) structure in sub 20nm DRAM.