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1-8 of 8
Kristofor Dickson
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Proceedings Papers
ISTFA2024, ISTFA 2024: Conference Proceedings from the 50th International Symposium for Testing and Failure Analysis, 377-384, October 28–November 1, 2024,
Abstract
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This paper describes how lock-in amplifiers and boxcar averaging can overcome limitations in conventional fault isolation techniques for microelectronic testing. Our approach achieves superior results compared to traditional spectrum analyzer methods through three key applications. First, we measure the signal-to-noise ratio of individual pulses during laser voltage tracing (LVT) across varying pulse widths. Second, we leverage enhanced LVT imaging to improve computer-aided design to stage alignment and laser voltage probe placement—a crucial advancement for analyzing compressed scan and streaming scan network test failures. Finally, we present a case where our Lock-In amplifier system successfully generates pass/fail signals for dynamic laser stimulation in scenarios where conventional test hardware proved inadequate.
Proceedings Papers
ISTFA2024, ISTFA 2024: Conference Proceedings from the 50th International Symposium for Testing and Failure Analysis, 385-391, October 28–November 1, 2024,
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Secure edge devices and the need for hardware security are of paramount importance due to the growing demand for cybersecurity. Hardware security has been strengthened using complex architecture to provide uncompromisable security and prevent malicious cybersecurity attacks. To prevent unauthorized access using even the most advanced failure analysis (FA) techniques, the Hardware Security Module (HSM) implements cryptographic algorithms and data obfuscation using many raw combinational logic and state machines. When a newly taped-out device fails to operate or fails to come out of its secure boot-up sequence, how can we know whether a defect is present or if the security block reacted to a design error? This paper discusses various real-world examples of FA challenges related to first silicon debug, including secure IP. We explore the unique approaches required to make sense of collected Laser Voltage Probe (LVP), Photon Emission Microscopy (PEM), and Laser Logic State Mapping (LLSM) data. We discuss some of the most advanced FA techniques' strengths and weaknesses and illustrate how system architecture related to securing data can be modified to alter the effectiveness of each. We explain in detail why specific FA techniques can be defeated by built-in security and where FA techniques can be enabled by clever triggering schemes or looping on areas of code while looking for specific behaviors. This paper also talks about the limitations of analyzing complex architecture being good from a security point of view. We conclude by summarizing the threat FA tools present to secure IP and comment on steps that could be taken to further protect internal state machines and sensitive logic areas from even the most well-equipped FA labs. Thus, this work gives an introspective thought as to how Optical Fault Isolation (OFI) techniques could be perceived as a threat to various security applications and points to trade-offs between the ability to analyze versus hardware security.
Journal Articles
Journal: EDFA Technical Articles
EDFA Technical Articles (2024) 26 (2): 32–38.
Published: 01 May 2024
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Differential laser voltage probe simultaneously acquires waveform data from a single target while the device under test fluctuates between passing and failing test outcomes. This article describes the use of this technique and how it could be affected by trends in the microelectronics industry.
Proceedings Papers
ISTFA2023, ISTFA 2023: Conference Proceedings from the 49th International Symposium for Testing and Failure Analysis, 54-61, November 12–16, 2023,
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Hard failures, especially the Stuck at Reset failures insensitive to voltage, frequency, and temperature, are among the toughest to debug using the conventional Electrical Fault Isolation Methodology. These types of failures have no test data and no diagnostic information. Because of the failure being stuck at the reset sequence and being a hard failure, methodologies like Laser-Assisted Device Alteration (LADA) cannot be carried out. Photon Emission Microscopy (PEM) may exhibit numerous differences for good vs. bad die, however, most emission signatures typically indicate where IP is stuck in reset but do not indicate the actual root cause. Laser Voltage Probe (LVP) is the most logical way to proceed, but since Power-on Reset (POR) signals typically transition only once per test in conjunction with hard power cycling, the LVP averaging became very difficult as the hard power cycling increased the time of the loop drastically. This paper discusses a novel methodology of modulating power supply voltages within a looping pattern to optically probe the critical internal POR signal transitions effectively and debug the power sequencing of the device. This method is carried out through a custom test setup where a particular power supply of interest is modulated within the test loop without powering down other supplies connected, thereby avoiding the time penalty required for complete power down and power up. The method also synchronizes internal signals associated with POR to a tester-generated trigger in order to successfully obtain recognizable internally extracted POR-associated waveforms. This methodology is conveyed by explaining a complex functional failure analysis case study while highlighting where conventional failure analysis methods could not be used directly to identify the root cause of failure. This paper also describes another case study to explain how parametric information, such as the current profile using the current probe obtained during the test on a pass vs. fail device, can provide valuable information and help debug stuck-in reset failures.
Proceedings Papers
ISTFA2023, ISTFA 2023: Conference Proceedings from the 49th International Symposium for Testing and Failure Analysis, 403-410, November 12–16, 2023,
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In this work, we present three case studies that highlight the novelty and effectiveness of using multiple plasma FIB trenches to simultaneously access multiple metal layers for nanoprobing failure analysis. Multilayer access enabled otherwise impossible two-tip current imaging techniques and allowed us to fully characterize suspect logic gate transistors by exposing internal nodes, while preserving higher metal inputs and outputs. The presented case studies focus on late node planar and established FinFET technologies. The delayering techniques used are not necessarily technology dependent, but highly scaled and advanced processes generally require smaller trench areas for multilayer access. The minimum trench dimensions are limited by ion beam imaging resolution and trench-nanoprobe tip geometry.
Series: ASM Technical Books
Publisher: ASM International
Published: 01 November 2023
DOI: 10.31399/asm.tb.edfatr.t56090003
EISBN: 978-1-62708-462-8
Abstract
This chapter assesses the capabilities and limitations of electric fault isolation (EFI) technology, the measurement challenges associated with new device architectures, and the pathways for improvement in emission microscopy, laser stimulation, and optical probing. It also assesses the factors that influence signal strength, spatial and timing resolution, and alignment accuracy between signal response images and the physical layout of the IC.
Proceedings Papers
ISTFA2022, ISTFA 2022: Conference Proceedings from the 48th International Symposium for Testing and Failure Analysis, 144-152, October 30–November 3, 2022,
Abstract
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Laser Voltage Probing (LVP) is an essential Failure Analysis (FA) technique that has been widely adopted by the industry. Waveforms that are collected allow for the analyst to understand various internal failure modes related to timing or abnormal circuit behavior. As technology nodes shrink to the point where multiple transistors reside within the diffraction-limited laser spot size, interpretation of the waveforms can become extremely difficult. In this paper we discuss some of the evolving challenges faced by LVP and propose a new technique known as Differential LVP (dLVP) that can be used to debug marginal failing devices that exhibit a pass/fail boundary in their shmoo plot. We demonstrate how separate pass and fail LVP waveforms can be collected simultaneously and compared to immediately identify whether logic is corrupted and when the corruption occurs. The benefits of this new technique are many. They include guarantees of equivalent pass vs. fail data independent of crosstalk, system noise, stage drift, probe placement, temperature effects, or the diffraction-limited resolution of the probe system. Implementing dLVP into existing tools could extend their effective lifetimes and improve their efficacy related to the demands posed by the debug of 5nm technologies and smaller geometries. We anticipate that fully integrated and evolved dLVP will complement workhorse FA applications such as Laser Assisted Device Alteration (LADA) and Soft Defect Localization (SDL) analysis. Wherein those techniques map timing marginalities propagating to, and observed by, a capture flop, dLVP can extend such capabilities by identifying the first instance of corrupted logic inside the flop and map the corruption all the way to the chip output pin.
Proceedings Papers
ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 48-52, November 10–14, 2019,
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Failure analysis on mixed-signal ICs for automotive applications often requires the use of EVBs (evaluation boards) to replicate the failure mode. Typically, automotive ICs are used in conjunction with other components to create automotive modules, such as; PCM (power-train control modules), ECU (engine control units), TCU (transmission control units), etc. EVBs are used to replicate module level functionality, as well as reproduce ATE (automatic test equipment) tests required for analysis. An integral part of EVB design, functionality and performance is related to the IC socket, which is the direct interface between the IC and the EVB. See Figure 1. EVB socket solutions will vary based on the required analysis (backside / topside analysis), package type and IC functionality.