It is necessary for space applications to evaluate the sensitivity of electronic devices to radiations. It was demonstrated that radiations can cause different types of effects to the devices and possibly damage them [1][2]. The interest in the effect of Single Event Transient (SET) has recently risen because of the increased ability of parasitic signals to propagate through advanced circuit with gate lengths shorter than 0.65 nm and to reach memory elements (in this case they become Single Event Upset (SEUs)). Analog devices are especially susceptible to perturbations by such events which can induce severe consequences, from simple artifacts up to the permanent fail of the device. This kinds of phenomena are very difficult to detect and to acquire, because they are not periodical. Furthermore, they can vary a lot depending on different parameters such as device technology and biasing. The main obstacle for the analysis is due to the maximum frequency of these signals, which is unknown. It is consequently difficult to set a correct sample frequency for the acquisition system. In this document a methodology to evaluate SETs in analog devices is presented. This method allows to acquire automatically these events and to easily study the sensitivity of the device by analyzing a “SETs cartography”. The advantages are different: it allows to easily acquire and analyze the SETs in an automatic way; the obtained results allow the user to accurately characterize the device under test; and, finally, the costs due to the implementation of the tests are lower than a classical analysis performed by a particle accelerator.

VLSI internal testing through silicon substrate has been widely studied and techniques like Time Resolved Emission has given impressive results. Nevertheless, Integrated Circuits (IC) are still evolving with more and more complex functions and various kinds of signals that could be split into two main categories: data and control. Controls activate specific block and according to the wide range of different blocks and device complexity, the first analysis task is to check block activity related to control line status. In this paper, we show how Time Resolved Imaging can precisely answer this challenge even in up-to-date technologies at low power supply.

The failure localization on analog & mixed mode ICs in functional mode (AC signals) has become more and more challenging in the last few years. Due to an increasing integration and complexity of these devices, the number of defects, especially those named “soft”, raised considerably. The classical Dynamic Laser Stimulation (DLS) techniques showed some limitations when applied to analog & mixedmode ICs. The SDL (Soft Defect Localization) technique [1] based on binary output signal allows us to localize only the most sensitive areas. The defect in this type of circuits, which are very sensitive to the laser beam [2], is often characterized by a weaker sensitivity than that of “healthy” regions. Hence, xVM (Variation Mapping) techniques were introduced to map some parameters in an analog way (the different sensitivity levels are visualized). To date, the T-LSIM technique [3], the Delay and the Phase Variation Mapping techniques were published [4, 5]. We have already had some interesting results by using these techniques [6] but not every “soft” defect case study could be resolved in that way. In this paper we propose to look at some different parameters which characterize an analog signal and can be used as an input for laser mapping. By applying a simple setup, without any additional sophisticated tool, we show on a “golden” commercial IC the added value of this analysis. We also deal with amplifying the weak signal variations induced by the laser beam scan which often are hidden by the high signal variations in analog or mixed-mode ICs.

Soft defect localization techniques based on laser stimulation have become key techniques for a wide range of FA/debug issues. In this paper, we demonstrate the ability of these techniques to solve critical design issue in mixed-mode device for automotive application which includes analog, logic, RF and power. Utilizing a wide range of laser stimulation techniques, we have determined the most efficient approach for this device to achieve the shortest cycle time. We have established a clear link between fault isolation by laser stimulation techniques and the abnormal behavior of the device with relevant and complete simulation at transistor level.

In this paper we report on the application field of Dynamic Laser Stimulation (DLS) techniques to Integrated Circuit (IC) analysis. The effects of thermal and photoelectric laser stimulation on ICs are presented. Implementations, practical considerations and applications are presented for techniques based on functional tests like Soft Defect Localization (SDL) and Laser Assisted Device Alteration (LADA). A new methodology, Delay Variation Mapping (DVM), will also be presented and discussed.