Scanning Capacitance Microscopy (SCM) is an essential technique in semiconductor failure analysis. It is widely known in studies of dopant profiles and carrier concentration. Not only that, SCM can be utilized as an electrical fault isolation tool to localize a failing transistor. Compared to Conductive Atomic Force Microscopy CAFM, the main advantage of SCM is that it can be used on both Silicon on Insulator (SOI) and Bulk Silicon wafers. In addition, SCM can scan over a relatively large area in a shorter time than conventional nanoprobing methods. This paper presents case studies illustrating the effectiveness of SCM for die level top-down failure analysis on 45nm node SOI and 14nm FinFET bulk Si technologies.

This study investigates the application of 3D electron tomography to enhance transmission electron microscopy (TEM)-based failure analysis of 3D FinFET transistors. Traditional TEM analysis is challenged by projection effects due to the thickness of the sample, complicating accurate defect characterization in miniaturized semiconductor structures. The defects seen by conventional (2D projection) TEM imaging are unclear and difficult to interpret. Leveraging scanning transmission electron microscopy (STEM) and energy dispersive X-ray spectroscopy (EDS) tomography techniques, the study presents detailed examinations of two semiconductor samples exhibiting high leakage currents. Results reveal etched-out epitaxial regions subsequently filled with gate materials, critical for understanding device failure. By digitally reconstructing TEM lamellae in three dimensions, this approach overcomes projection artifacts and precisely localizes defects. The findings underscore the efficacy of 3D electron tomography in semiconductor failure analysis, offering insights crucial for improving device reliability and manufacturing processes in advanced semiconductor technologies.

This paper demonstrates capacitance-voltage (CV) measurements using Nanoprobing to characterize different fails and better understand the defect mode. Three case studies are conducted using the CV technique. DC Nanoprobing measurements are first used to identify the failure mode. Subsequently, CV measurements are employed to further narrow down the root cause, to understand the process mechanism leading to the failure. A pathway to use the CV technique to isolate defects with-in a device under test is also demonstrated. It has been shown that the gate to lightly doped drain CV measurements will be a very useful characterization tool to understand various fail modes. This finding, along with DC measurement, serves to narrow the issue primarily to gate stack work function related matters.

Massively parallel test structures, based on looking for shorts between certain design elements in the SRAM cells, are becoming increasingly relied upon in yield characterization. The localization of electrical shorts in these structures has posed significant challenges in advanced technology nodes, due to the size, and design complexity. Several of the traditional methods (nanoprobing, OBIRCH, etc.) are shown to be inadequate to find defects in SRAM cells, either due to resolution, or time required. In recent years, the Electron Beam Induced Resistance Change (EBIRCH) technique has increasingly been utilized for failure analysis. Combining EBIRCH with other techniques, such as SEM based nanoprobing system and PVC, allows not only direct electrical characterization of suspicious bridging sites but also allows engineers to pinpoint the exact location of defects with SEM resolution. This paper will demonstrate the several cases where SRAM-like test structures provided extreme challenges, and EBIRCH was the key technique towards finding the fail. A node to node, node to wordline, and ground-ground contact fails are presented. A combination of EBIRCH with the more traditional techniques in advanced technology node is key to timely and accurate determination of shorting mechanisms in our test structures.

OBIRCH is a static technique for isolating both high and low resistance failures in test structures that continues to be relevant to sub 14nm technologies. While limited resolution is a factor as devices get smaller, an approximate location is adequate for finding obvious defects on sub 14nm technology structures. Its speed is what makes this technique appealing. If the approximate location isn’t good enough, a more time-consuming, higher-resolution technique can be employed. But the use of OBIRCH as a first isolation technique saves considerable time for a high volume FA lab if obvious defects cause the majority of failures. The seven case studies on sub 14nm technology are examples of obvious defects where OBIRCH had adequate resolution for isolation. The OBIRCH results for the first example are compared to the PVC (Passive Voltage Contrast) and EBAC (Electron-Beam Absorbed Current Imaging) findings to illustrate each technique’s strength and weakness.

Nanoprobing, electrical probing (DC electrical measurement of semiconductors using nanoscale probes) on an electron microscopic scale, and EBAC, a high-resolution, static technique, can be used for isolating defects and improving failure analysis success rates on both logic and SRAM devices. This paper presents three case studies of subtle defects on a technology beyond 14nm that required nanoprobing.

EBAC is a high-resolution, static technique that can be used for isolating electrical shorts, but it begins to fail for large, interconnected, test structures. In such cases, localization can be achieved when combined with optical localization techniques such as OBIRCH. This paper presents two case studies of subtle, FEOL shorts on a sub-14nm technology that required the resolution of EBAC.

The advances on IC technology have made defect localization extremely challenging. “Soft” failures (resistive vias and contacts) are typically difficult to localize using commonly available failure analysis (FA) techniques such as emission microscopy (EMMI) and scanning optical microscopy (SOM), and often cannot be observed by two-dimensional inspections using layer by layer removal. The article describes the Resistive Contrast Imaging (RCI) defect localization technique (also known as Electron Beam Absorbed Current (EBAC), instrumentations, and case studies on test structures or process control monitors especially designed to detect “soft” open failures on advanced (28nm and below) technology devices. It also lists the key SEM parameters critical for effective FA using the RCI nano-probing system.