Packages with the Modified Daisy-chain (MDC) die have been used increasingly to accelerate reliability stress testing of IC packaging during package development, qualification, and evaluation and reliability monitor programs [1]. Utilizing this approach in essence eliminates chip circuit failure mechanisms. Unlike packages with active die, in packages with the MDC die, when short occurred between two daisy-chain pairs of I/Os, there are four possibilities that can attribute to each pin of the two daisy-chain pairs. That makes the isolation of short failure difficult. Time Domain Reflectometry (TDR) is a well-described technique to characterize package discontinuity (open or short failure). By using a bare package substrate and a reference device, an analyst can characterize the discontinuity and localize it: within the package, the die-package interconnects, or on the die [2]. Scanning SQUID (Superconducting Quantum Interference Device) Microscopy, known as SSM, is a non-destructive technique that detects magnetic fields generated by current. The magnetic field, when converted to current density via Fast Fourier Transform (FFT), is particularly useful to detect shorts and high resistance (HR) defects [3]. In this paper, a new methodology that combines Resistance Analysis, TDR Isolation and SSM Identification for electrical debugging short in packages with the MDC die will be presented. Case studies will also be discussed.

Scanning acoustic microscopy (SAM) is a non-destructive tool for analysis of packaged devices. New materials, package configurations, and technologies have required adaptation of standard practices in SAM. The detection of cracked die, voids, or delamination in the underfill or package are standard issues for SAM. SAM can routinely detect large cracks through the central 80% of the die; however, the occurrence of smaller cracks at the edge of the flip chip die is problematic. This article proposes a model in which alteration in the standard SAM parameters, the gain and Time-of-Flight, enable detection of die edge cracks in assembled Flip Chip devices. IR imaging after thinning and polishing of the die confirms the die edge cracks. The SAM analysis can replace the IR imaging for detection of small die edge cracks taking minutes to complete instead of the hours involved in the sample preparation for IR imaging.

Driven by ever increasing pin-counts and device performance, analyses of multi-layer package substrate failures are increasingly challenging. The tried method of global deprocessing delivers diminishing returns. Increasingly, an entire suite of specialized package analysis tools is needed to complement each other and achieve root-cause.

Scanning SQUID (Superconducting Quantum Interference Device) Microscopy, known as SSM, is a non-destructive technique that detects magnetic fields in Integrated Circuits (IC). The magnetic field, when converted to current density via Fast Fourier Transform (FFT), is particularly useful to detect shorts and high resistance (HR) defects. A short between two wires or layers will cause the current to diverge from the path the designer intended. An analyst can see where the current is not matching the design, thereby easily localizing the fault. Many defects occur between or under metal layers that make it impossible using visible light or infrared emission detecting equipment to locate the defect. SSM is the only tool that can detect signals from defects under metal layers, since magnetic fields are not affected by them. New analysis software makes it possible for the analyst to overlay design layouts, such as CAD Knights, directly onto the current paths found by the SSM. In this paper, we present four case studies where SSM successfully localized short faults in advanced wire-bond and flip-chip packages after other fault analysis methods failed to locate the defects.

Two novel techniques to identify continuity failures in multi-layer substrates of flip-chip package are discussed. The first technique uses the custom designed and fabricated Package Substrate Probe Fixture (PSPF™). The fixture eliminates the traditional method of soldering directly to the package solder balls. This ensures that failures are not heat cured and the solder ball as well as the Ball Grid Array (BGA) pad are not detached from the package substrate during physical analysis. Also employed are beam-based systems that include both Focused Ion Beam (FIB) and Electron-beam (Ebeam) to detect Capacitive Coupling Voltage Contrast (CCVC) images. Voltage contrast imaging augments traditional optical inspection techniques using bright and dark field microscopy.