This article explores the use of principal component analysis (PCA) and hierarchical clustering in the analysis of wafer level automatic test pattern generation (ATPG) failure data. The principle of commonality is extended by utilizing hierarchical clustering to collect die that are more similar to one another in their manner of failure than to others. Similarity is established by PCA of the patterns that the die in a wafer fail. Results demonstrated that PCA analysis and clustering are useful tools for dimensionality reduction and commonality analysis of wafer level ATPG data. The utility of PCA analysis and clustering in the extraction of die for physical failure analysis is also illustrated.

This paper describes the use of image processing techniques in metrology and failure analysis with the help of three case studies. The first study concerns a technique that significantly automates the process and hence enables both a rapid and accurate extraction of cumulative distribution function for transistor CD through the use of edge detection and quantification of image intensities. The second study is about utilizing a cross correlation algorithm and an appropriately chosen sample and image to estimate the "on image" spatial resolution of an scanning electron microscope. The last case study uses image data acquired with an atomic force microscope. The paper describes how information theoretic concepts like entropy and mutual information combined with image segmentation and nearest neighbor extraction can be used to isolate those regions of the AFM scan that can potentially benefit from further analysis.

Precise fail site isolation plays a very important role today in the world of semiconductors. Its importance increases more, as the devices are of cutting edge technology with increasing complexity and decreasing dimensions. Global fail site isolations techniques (like XIVA, Photo Emission, FMI etc) and tester based techniques (using automatic test equipment, Fastscan etc) alone, are no longer sufficient and may not be successful. Long net lists and large fail sites isolated by these methods pose problems for physical failure analysis. Planarity of these large areas during parallel lap and inspection times using the SEM is difficult and tedious, thus leading to long cycle times and low resolution rates. There exists a need for precise fail site isolation. In many cases, no single technique can be used to narrow down a fail site significantly. Instead a combination of different techniques must be used. In this paper we present a case study, where a combination of complimentary techniques are used to successfully isolate a fail area of more than 1300 microns in length to less than 100 microns on a single failing net.

Traditionally, planar scanning capacitance microscopy has been conducted on samples which have been deprocessed to the level of the substrate and an oxide re-grown over the sample. However, HF used to etch the sample to the substrate can also dissolve shallow junctions. This article documents the ability of scanning capacitance microscopy to be utilized at the level of the contacts leaving the pre-metal dielectric intact. It demonstrates the scalability of this technique across three process generations spanning 0.18 micron, 0.13 micron, and 90 nm nodes. The article documents preliminary data on anomalous contrast observed in contacts at both 0.13 micron node and 90 nm node products. It also demonstrates the ability to distinguish between contacts going to a n-type diffusion, p-type diffusion, and transistor gate. The article also presents a simple model for the CV curves of defective contacts to source/drain diffusions.

Chip access for flip-chip packages in high-performance microprocessors is performed by removing the lid then by extraction of the die from the package substrate. Residual stresses built in temperature cycled (TC) units result in a low success rate using conventional delidding techniques. A need has developed in failure analysis for stress-free removal of the materials surrounding a flip-chip device. This paper discusses a novel, cost effective, wet chemical process that has been developed for thin die and lid removal of flip-chip packaged units. The process uses n-methy-2-pyrrolidone (NMP) for epoxy-based lid attach and underfill materials. A reflux unit is designed to reduce the risk of fire and explosion when the sample is heated in the solvent to the desired temperature. The method of heating reduces the chance of thermal shock, which could fracture the sample due to rapid heating or cooling.

Solder bumps are frequently the sites of defects that cause continuity failures in ceramic flip chip packages. In concurrent technology the solder bump is a multi-layered structure containing several interfaces. Conventional c-SAM imaging alone cannot delineate subtle bump defects. In this article we present experimental results that document the nature of interface defects in multi-layered solder bumps as well as their acoustic signatures. The acoustic signatures obtained from defective bumps are contrasted with the signals obtained from pristine bumps and the sensitive nature of these signatures to defects is highlighted.

Optical waveform probing is a critical component in flipchip diagnostics. There is a dramatic increase in the need for backside silicon probing of non-flipchip packaged devices. The effective way to implement this strategy is to package the die in a BGA carrier that allows backside analysis. Optical waveform probing has been used primarily as a digital waveform timing analysis tool. The capability of optical waveform probers can be extended to failsite isolation and qualitative analog signal analysis.

In the current generations of devices the die and its package are closely integrated to achieve desired performance and form factor. As a result, localization of continuity failures to either the die or the package is a challenging step in failure analysis of such devices. Time Domain Reflectometry [1] (TDR) is used to localize continuity failures. However the accuracy of measurement with TDR is inadequate for effective localization of the failsite. Additionally, this technique does not provide direct 3-Dimenstional information about the location of the defect. Super-conducting Quantum Interference Device (SQUID) Microscope is useful in localizing shorts in packages [2]. SQUID microscope can localize defects to within 5um in the X and Y directions and 35um in the Z direction. This accuracy is valuable in precise localization of the failsite within the die, package or the interfacial region in flipchip assemblies.