For fault management, various types of error-correcting codes (ECC) have been widely used for most computers and memory. From a memory perspective, the ECC technique is generally adopted for DRAM modules to correct data corruption among multiple chips, not in-chip level. Recently, increased soft single-bit failures have accelerated introduction of the ECC technique into DRAM components. For reliability, fault generation technique by high voltage at high temperature, also known as burn-in stress, has been widely used in the IC manufacturing process. In DRAM, burn-in stress is also useful to screen latent defects or to predict device lifetime. In this paper, we studied un-correctable errors which occurred due to various types of storage node bridge defects in ECC DRAM. 12 faulty cells among 1,000 cells are observed after burn-in stress. Retention time of each cell is measured with automatic test equipment under the various temperature conditions, and activation energy were extracted from measurement results. Results of activation energy show that there were two types of faults, one was metal-metal hard bridge (0.14eV) and the other was dielectric-dielectric soft bridge (0.35eV), in comparison with normal cells (0.53eV). Moreover, soft bridge was carefully analyzed with TEM and nanoprobing showing that activation energy analysis was well-matched.

As various types of DRAM package have been developed, new defects in interconnection in chip have been discovered after assembly process such as flip chip bump mount or wire bonding. There are lots of regular inspections in manufacturing process to detect assembly defects, but it is not easy to find all of the defects. We used a method to classify physical failures based on electrical measurements. Conventional open and short tests by using ISVM were used to support the mass production. External voltage sweep is employed to distinguish weak defects from strong defects of interconnection. Finally, a proposed method was verified with statistical analysis of 800,000 FBGA DRAM chips and physical analysis of failure chips.

System failure due to a progressive defect in memory cell-array of DRAM was studied with automated test equipment. In order to find out relationship correctable single-bit fault and system failure, memory cells with single-bit fault by a cross-defect were selected. After high voltage and temperature stress, a soft cross-defect was changed into a hard cross-defect. Consequentially, invalid operation by a degraded cross-defect causes array-failure. Based on the failure analysis, methods to prevent array-failure are proposed, and applied to DRAM successfully.

As the DRAM structure is miniaturized, the cell capacitance is reduced and resistance is increased. Because of this change, the DRAM operation is more sensitive than previous generations to changes of the device elements. The device elements consist of cell capacitance, Bit Line (BL) capacitance, cell node resistance, supply-voltage and the surround noise. The elements were changed by decreasing the cell node dimensions. The write time (tWR) is degraded by changing the elements. In particular, the noise is very variable element on change of surrounding cell phase which is data1 or data 0. In this paper, we show that one of the most dominant contributors to failure is the plate noise and explain how plate voltage level affects tWR delay. The effect of the plate voltage modulation can be correlated with ∆Vbl which is bit line level difference to read out the data. We define this phenomenon as the plate dc noise effect and propose a model in miniaturized DRAM.

Systematic retention failure related on the adjacent electrostatic potential is studied with sub 20nm DRAM. Unlike traditional retention failures which are caused by gate induced drain leakage or junction leakage, this failure is influenced by the combination of adjacent signal line and adjacent contact node voltage. As the critical dimension between adjacent active and the adjacent signal line and contact node is scaled down, the effect of electric field caused by adjacent node on storage node is increased gradually. In this paper, we will show that the relationship between the combination electric field of adjacent nodes and the data retention characteristics and we will demonstrate the mechanism based on the electrical analysis and 3D TCAD simulation simultaneously.

As microelectronic feature sizes are scaled down, the soft failure rate has increased. Additionally the characteristics and distribution of Dynamic Random Access Memory (DRAM) data retention time and write recovery time (tWR) are getting worse. As a result of this failure analysis, we revealed that the major contributors are caused by the interference noise, resultant from decreasing separation distance between nodes and the signal line noise increasing. This paper gives a detailed analysis of the problem caused by the coupling effects. We investigated the cause of soft noise by simulation and proposed calculation of sensing margin change by interference noise. Finally, we expect that a design improvement to reduce the magnitude of interference noise will result in overall improvement when implemented in the test vehicle.

As microelectronic feature sizes are scaled down, the characteristics and distribution of DRAM data retention time and write recovery time are getting worse. This degradation is due to the increases in the leakage current and resistance of the cell node and the decrease of cell capacitance in DRAM devices. As the physical distance between storage nodes decreases, node potential is increasingly affected by small potential changes in adjacent storage nodes. In this paper, we will show that the one of the most dominant contributors to failure is the adjacent storage node level, and we will demonstrate how node level affects write time delay. The effect of the adjacent storage node level can be correlated with a change in threshold voltage, much like the MOSFET body effect. We define this phenomenon as the lateral body effect, and propose a model for adjacent potential effect using the Buried Cell Array Transistor (BCAT) structure in sub 20nm DRAM.

The open bit line architecture scheme is an effective method to achieve higher density memory devices. With the scaling of DRAM, we have adopted a bit line sense amplifier (BLSA) design using a shared local power line for reducing the circuit layout dimensions. As a result of this new design, the write time of the memory cell was sometimes degraded because of an increase in initial sensing noise. This paper gives a detailed analysis of the problem caused by the initial sensing noise by examination of the behaviour of the opposite data portion of the cell array matrix when the word line is not activated. Finally, we propose a design improvement to reduce the magnitude of noise peaks and the results of this improvement when implemented in the test vehicle.