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1-7 of 7
Kah Chin Cheong
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Proceedings Papers
ISTFA2023, ISTFA 2023: Conference Proceedings from the 49th International Symposium for Testing and Failure Analysis, 201-204, November 12–16, 2023,
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As technology nodes continue to shrink, Scanning Electron Microscopy (SEM) inspection and electrical characterization of transistors has increased in difficultly. This is particularly true with early back end-of-line (BEOL) features like metal and via layers which are traditionally imaged at 3-5 keV. At these layers, this energy is capable of beam contamination, introducing electrical complications particularly with transistor probing. This electrical data is necessary to characterize subtle defects at front end-of-line (FEOL). Thus, the implementation of beam deceleration for the inspection of these layers provides a useful combination of low landing energy and higher image quality. This technique proves to aid in preserving the ability to electrically characterize any defect at the subsequent layers beneath. This increases the quality of the Physical Failure Analysis (pFA) workflow when implemented at early BEOL layers by providing higher quality images as well as preserving the electrical properties of the transistors for subtle FEOL defect characterization.
Proceedings Papers
ISTFA2023, ISTFA 2023: Conference Proceedings from the 49th International Symposium for Testing and Failure Analysis, 295-299, November 12–16, 2023,
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In this paper, we discuss and showcase a 2-step defect isolation methodology by combining Focused Ion Beam “circuit editing” (FIB circuit edit) and Passive Voltage Contrast (PVC) imaging. The combo technique is an effective, robust, and time saving method for isolating defects in large area circuit structures for advanced nodes. The application of FIB circuit edits successfully enhanced the PVC efficiency in defect isolation. More importantly, the developed 2-step methodology improves failure analysis (FA) success rate and quality, and reduces FA turn-aroundtime (TAT).
Proceedings Papers
ISTFA2022, ISTFA 2022: Conference Proceedings from the 48th International Symposium for Testing and Failure Analysis, 347-351, October 30–November 3, 2022,
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Passive voltage contrast (PVC) is a well-known fault isolation technique in differentiating contrast at via/metal/contact levels while focused ion beam (FIB) is a destructive technique specifically used for cross sectioning once a defect is identified. In this study, we highlight a combination technique of PVC and progressive FIB milling on advanced node fin field-effect transistor (FinFET) for root cause analysis. This combo technique is useful when applied on high-density static random access memory (SRAM) structure, especially when it is difficult to view the defect from top-down inspection. In this paper, we create a FA flow chart and FIB deposition/milling recipe for SRAM failure and successfully apply them to three case studies.
Proceedings Papers
ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, 269-273, October 31–November 4, 2021,
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Planar deprocessing is a vital failure analysis technique for semiconductor devices. The basic concept is to expose an area of interest (AOI) by removing unnecessary material while maintaining planarity and surface evenness. Finger deprocessing is a widely used material removal technique, particularly for fin field-effect transistors (FinFETs). Here, success depends on certain factors, one of which is the location of the AOI. If the AOI is near the edge of the chip, finger deprocessing can be very difficult because material removal rates are much higher there than at the center of the chip. Plasma focused ion beam (PFIB) planar deprocessing is the preferred solution in such cases, but many labs cannot afford a PFIB system. To address this challenge, a sample preparation method has been developed that uses dummy chips to effectively eliminate edges. With dummy chips placed edge-to-edge with test chips, planar deprocessing can be achieved using conventional finger deprocessing techniques. This paper describes the newly developed method, step by step, and presents two examples demonstrating its use.
Proceedings Papers
ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 372-376, November 10–14, 2019,
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This paper demonstrates a two-pin Electron Beam Induced Current (EBIC) isolation technique to isolate the defective Fin with gate oxide damage in advanced Fin Field Effect Transistor (FinFET) devices. The basic principle of this twopin configuration is similar to two-point Electron Beam Absorption Current (EBAC) technique: a second pin as ground on the gate is added to partially shunt the EBIC current and thus creates EBIC contrast from the defective Fin. In this way, the challenge of highly resistive short path inside the Fin in a narrow gate can be overcome. The paper will provide failure analysis details using this technique for defective Fin isolation.
Proceedings Papers
ISTFA2017, ISTFA 2017: Conference Proceedings from the 43rd International Symposium for Testing and Failure Analysis, 585-591, November 5–9, 2017,
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The application of underfill materials for board level assembly has been increasing rapidly in semiconductor industry to enhance strength and reliability performance of semiconductor components in harsh environments. However, due to the intractability of the capillary underfill after curing, extracting a chip scale package (CSP) device from a printed circuit board (PCB) with a combination of mold compound and capillary underfill for ATE testing has become difficult and challenging. This poses a severe limitation to this technology regarding electrical testing and failure analysis. In order to address the challenge in extracting a CSP device from an underfilled PCB without inducing any mechanical damage, a series of sample preparation techniques has been introduced. This paper discusses the techniques in removing the fine pitch CSP device from underfilled PCB module in a relatively simple way which includes application of chemical solutions, de-soldering, residual solder remnants cleaning and reballing. The established process enables ATE testing, electrical testing and failure analysis to be performed on any CSP devices. An electrical evaluation on the efficiency of a CSP device after a series of sample preparation processes will also be highlighted.
Proceedings Papers
ISTFA2016, ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis, 175-181, November 6–10, 2016,
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Copper pillar WLCSP device embedded in large PCB module with passive devices to create one hybrid package are growing widely in smart communication and mobile electronic devices. The crucial challenges in electrical testing and failure analysis on it are to remove the embedded copper pillar CSP device from the module without inducing mechanical defects, and solder ball placement on the CSP for ATE testing. This paper discusses the sample preparation process step-by-step, which includes de-soldering of external components from the PCB, top side up and down parallel polishing to remove copper pillars, chemical etching the PCB module, solder ball placement on CSP devices and the soldering process on a plain coupon board. The established process enables electrical testing, evaluations and failure analysis performed on a demounted CSP device. A simulation of an electrical testing and failure analysis will also be highlighted in this paper.