A successful failure analysis not only depends on extensive electrical and physical fault isolation by using all the advanced FA tools to narrow down the possible failure site, but also relies on actual physical defect findings. For advanced IC devices with technologies approaching sub-10nm and more than 10 layers of metallization built in ultra-low k materials, finding convincing physical defects becomes increasingly challenging. Backside deprocessing to reveal the physical defects at the active circuit layers and interconnect layers have been mostly done with KOH or TMAH as bulk Si etching chemicals, and some successful results have been published in the literatures. However, some challenges are also reported using these chemicals to achieve satisfactory results. In this paper, an improved backside deprocessing technique will be discussed using a special bulk Si etching chemical, choline hydroxide, to successfully reveal the physical defects on advanced IC devices. The new technique showed advantages over the existing techniques with more predictable and reliable results for backside deprocessing work. Two case studies will also be shared to demonstrate how this improved technique has been utilized to successfully reveal the physical damage at transistor gate level on the advanced MCU devices.

In this work we present a new defect localization capability on Wafer Level Chip Scale Packages (WLCSP) with small-scale Cu pillars using advanced 3D X-ray microscopy (XRM). In comparison to conventional microcomputed tomography (Micro-CT or microCT) flat-panel technology, the synchrotron-based optically enhanced 3D X-ray microscopy can detect very small defects with submicron resolutions. Two case studies on actual failures (one from the assembly process and one from reliability testing) will be discussed to demonstrate this powerful defect localization technique. Using the tool has helped speed up the failure analysis (FA) process by locating the defects non-destructively in a matter of hours instead of days or weeks as needed with destructive physical failure analysis.

C4 (Controlled Collapse Chip Connection) failure analysis compared to conventional packages (DIP- LCC- QFP, etc.) is not trivial. For instance, one has to thin the C4 die for IR microscope inspection or for photon emission analysis. Then, after failure analysis on the die, it must be removed for deprocessing or further analysis. Three methods and techniques will be discussed for removing the C4 die from the package without damaging the die. However, for each technique it is very important to know the condition of the die and package prior to die removal. The method used will differ, for example, if the die is thinned or not.