We present the first experimental demonstration of on demand bit-level Static Random Access Memory (SRAM) validation and isolation through the exploitation of a continuous wave (CW) 785nm Laser-Induced Fault Analysis (LIFA) system. Through careful test pattern edits and the observation of a simple pass/fail flag, the ability to spatially map the physical location of pre-selected bits in 40nm, 16nm, and 5nm SRAM arrays using correlation units is confirmed. This work demonstrates a novel and highly-efficient methodology for rapid bit-level logical-to-physical identification. It also improves localization efficacy over conventional bitmap validation best-known methods (BKM) which typically rely on post-fail Photo-Emission Microscopy (PEM) and/or Soft Defect Localization / Laser-Assisted Device Alteration (LADA) performed on an actual fail unit. This new technique re-defines the state-of-the-art in SRAM bitmap validation and localization and offers a pathway to significantly improve cycle time for both product bitmap qualification and subsequent root cause identification.

Laser Voltage Probing (LVP) is an essential Failure Analysis (FA) technique that has been widely adopted by the industry. Waveforms that are collected allow for the analyst to understand various internal failure modes related to timing or abnormal circuit behavior. As technology nodes shrink to the point where multiple transistors reside within the diffraction-limited laser spot size, interpretation of the waveforms can become extremely difficult. In this paper we discuss some of the evolving challenges faced by LVP and propose a new technique known as Differential LVP (dLVP) that can be used to debug marginal failing devices that exhibit a pass/fail boundary in their shmoo plot. We demonstrate how separate pass and fail LVP waveforms can be collected simultaneously and compared to immediately identify whether logic is corrupted and when the corruption occurs. The benefits of this new technique are many. They include guarantees of equivalent pass vs. fail data independent of crosstalk, system noise, stage drift, probe placement, temperature effects, or the diffraction-limited resolution of the probe system. Implementing dLVP into existing tools could extend their effective lifetimes and improve their efficacy related to the demands posed by the debug of 5nm technologies and smaller geometries. We anticipate that fully integrated and evolved dLVP will complement workhorse FA applications such as Laser Assisted Device Alteration (LADA) and Soft Defect Localization (SDL) analysis. Wherein those techniques map timing marginalities propagating to, and observed by, a capture flop, dLVP can extend such capabilities by identifying the first instance of corrupted logic inside the flop and map the corruption all the way to the chip output pin.