DRAM is a type of memory that stores each bit of data in a capacitor cell, leakage current is a very important electrical parameter to retain data. Therefore, larger cell capacitance and smaller leakage current have been regarded as key factors in continuous shrinkage of DRAM. Generally, gate induced drain leakage (GIDL) and junction leakage of cell transistor (CTR) are well-known, but our approach is focused on retention failure by bulk trap. In order to electrically observe the influence of bulk trap, we used the adjacent gate of CTR to control electron migration. Results show that there are many failure cells due to bulk trap, and dimension shrinkage accelerates this failure. Consequently, balancing among electrical bias point and transistor manufacturing process should be carefully considered with bulk traps.

There are many wafer level tests, such as Fail Bit Count (FBC), where conventional statistical analysis methods are inadequate because the associated data do not follow a normal distribution. This paper introduces a statistical failure analysis technique that does not rely on location and scale parameters and is thus able to handle such cases. It describes the math on which the method is based and explains how to determine effect size (ES) using the quantile comparison equivalence criteria (QCEC) and a statistical parameter, called the center of dispersion (CoD), that distinguishes between center difference and dispersion difference. It also includes a case study showing how the new method is used to assess the effect of a process change on dynamic random access memory test data and how it compares in terms of accuracy with conventional statistical techniques.