This article presents a step-by-step sample preparation method for the cross sectioning of silicon die in a ceramic package without the need for die removal or epoxy encapsulation. The sample preparation includes sawing the package, sample mounting to the polishing stub, and FIB cutting the area of interest and SEM Exam. In addition, a discussion on an automatic polishing method is included. This method is applicable for a broad range of silicon (Si) die package technologies and has also been successfully used on "TSOP" and state-of-the-art microprocessor packages which include the "organic" substrate, the Si die, and the massive copper die lid. The entire failure analysis is done at room temperature, eliminating any questions about sample preparation artifacts. Because the sample is imaged in the SEM at 90 degrees, much improved layer detail and voids microstructure is present in the final image.