Leakage current from bit line to SNC (Storage Node Contact) is one of the most critical issues in DRAM operation. Such failure becomes more difficult to visualize as the device shrinks. In this study, bit line to SNC leakage fail was analyzed using nano-probing tool in 2xnm DRAM technology.

It is important to understand the switching mechanism of phase change material for failure analysis of PRAM device. In this study, the real time observations of phase transition and void formation mechanism of confined GST structure were investigated using in-situ TEM with multi-pulse AC biasing technique. In-situ SET switching behavior between amorphous state and crystalline state with continuous structural change was successfully observed. Volume shrink of GST, due to the phase transition, induced voids at grain boundary of crystalline phase. Excess Joule-heating after crystallization caused coalescence and migration of voids. These results may give us a crucial clue for endurance failure analysis of PRAM.

We have demonstrated the sample fabrication by focused ion beam (FIB) milling and delineation etch gas which makes it possible to directly measure resistance in a cross section of semiconductor devices with a nano probe after cell fabrication. With direct evaluation of electrical properties, this technique can help improve semiconductor devices.