Tiny circuit design reliability issue related to competitive signal was investigated in a sense amplifier (SA) circuitry of SRAM by E-Beam probing technique in this paper. The irregular output signals then traced back to former stage circuit and identified associated waveforms. With such design concept and technique tracing, the invisible and cunning circuit mismatch reliability issue could be revealed successfully.

Scanning capacitance microscopy (SCM) is a 2-D carrier and/or dopant concentration profiling technique under development that utilizes the excellent spatial resolution of scanning probe microscopy. However, PV-SCM has limited capability to achieve the goal due to inherent "plane" trait. On top of that, deeper concentration profile just like deep N-well is also one of restrictions to use. For representing above contents more clearly, this paper presents a few cases that demonstrate the alternated and optimized application of PV-SCM and X-SCM. The case studies concern Joint Test Action Group failure and stand-by failure. These cases illustrate that the correct selection from either plane-view or cross-sectional SCM analysis according to the surrounding of defect could help to exactly and rapidly diagnose the failure mechanism. Alternating and optimizing PV-SCM and X-SCM techniques to navigate various implant issue could provide corrective actions that suit local circumstance of defects and identify the root cause.

Emission microscopy have been used for failure analysis (FA) defect isolation. But for advanced products, the working voltage of chip is getting smaller, thus many emission spots from normal transistors will be observed, which indeed affects the judgment on the emission spots from killer defects and increases the FA difficulty. Laser scanning microscope (LSM)-based techniques have been powerful defect isolation methods for many years. In this study, Checkpoint Infrascan 200TD, a laser-based tool, is used to perform defect localization. Here, thermally induced voltage alteration and optical beam induced resistance change are used to get defect locations. The study demonstrates three FA cases with 80nm/90nm technologies; metal direct short, poly leakage, and contact high resistance are also found in these cases. It is concluded that, by the selection of control parameters, Infrascan 200TD provides several capabilities of failure site localization and can be applied to different failure modes.

This article describes the electrical and physical analysis of gate leakage in nanometer transistors using conducting atomic force microscopy (C-AFM), nano-probing, transmission electron microscopy (TEM), and chemical decoration on simulated overstressed devices. A failure analysis case study involving a soft single bit failure is detailed. Following the nano-probing analysis, TEM cross sectioning of this failing device was performed. A voltage bias was applied to exaggerate the gate leakage site. Following this deliberate voltage overstress, a solution of boiling 10%wt KOH was used to etch decorate the gate leakage site followed by SEM inspection. Different transistor leakage behaviors can be identified with nano-probing measurements and then compared with simulation data for increased confidence in the failure analysis result. Nano-probing can be used to apply voltage stress on a transistor or a leakage path to worsen the weak point and then observe the leakage site easier.

In general failure analysis cases, a less invasive fault isolation approach can be utilized to resolve a visual root cause defect. In the case of nano technology, visual defects are not readily resolved, due to an increase in nonvisible defects. The nonvisible defects result in a lower success rate since conventional FA methods/tools are not efficient in identifying the failure root cause. For the advanced nanometer process, this phenomenon is becoming more common; therefore the utilization of advanced techniques are required to get more evidence to resolve the failure mechanism. The use of nanoprobe technology enables advanced device characterization in order to obtain more clues to the possible failure mechanism before utilizing the traditional physical failure analysis techniques.

The device features have shrunk to sub-micron/nano-meter range, and the process technology has been getting more complicated, so TEM has become a necessary tool for PFA imaging and element analysis. Conventional FIB ex-situ liftout is the most common technique for precise sample preparation. But this method has some limitations: samples cannot be reprocessed for further analysis; the carbon film supported grid affects the EDS analysis for carbon elements. A new installation will be introduced in this article, which is set up in FIB chamber for in-situ lift-out application. It not only overcomes the above problems, but also covers a wide application of TEM sample preparation.

As integrated circuits (IC) have become more complicated with device features shrinking into the deep sub-micron range, so the challenge of defect isolation has become more difficult. Many failure analysis (FA) techniques using optical/electron beam and scanning probe microscopy (SPM) have been developed to improve the capability of defect isolation. SPM provides topographic imaging coupled with a variety of material characterization information such as thermal, magnetic, electric, capacitance, resistance and current with nano-meter scale resolution. Conductive atomic force microscopy (C-AFM) has been widely used for electrical characterization of dielectric film and gate oxide integrity (GOI). In this work, C-AFM has been successfully employed to isolate defects in the contact level and to discriminate various contact types. The current mapping of C-AFM has the potential to identify micro-leaky contacts better than voltage contrast (VC) imaging in SEM. It also provides I/V information that is helpful to diagnose the failure mechanism by comparing I/V curves of different contact types. C-AFM is able to localize faulty contacts with pico-amp current range and to characterize failure with nano-meter scale lateral resolution. C-AFM should become an important technique for IC fault localization. FA examples of this technique will be discussed in the article.