In advanced chip package failure investigations, Electro Optical Terahertz Pulse Reflectometry (EOTPR) simulation emerges as a highly effective fault isolation technique. However, traditional manual methods for generating simulation models face significant challenges, including laboriousness, time consumption, and susceptibility to human error. To address these obstacles, we have developed an automation software script in-house. This script autonomously interfaces with the design database, extracting crucial trace information and generating an optimized equivalent trace model. This automated process markedly enhances the efficiency of EOTPR model simulations, streamlining workflow, standardizing procedures, and reducing the potential for human error. The efficacy of integrating the automation script into the workflow of advanced package failure analysis was demonstrated through two case studies. This integration significantly enhanced productivity and enabled successful root-cause investigation of advanced package failures.

The rapid development of advanced packaging technologies for high-performance computing (HPC) applications poses significant challenges for sample preparation methodologies. Conventional techniques are often insufficient to cope with the complex architectures and heterogeneous materials of modern packages, such as COWOS (Chip-on-Wafer-on-Substrate) and 3D structures. In this paper, we present a novel approach for sample preparation that leverages precision CNC (Computer Numerical Control) milling and selective MIP plasma etch. These methods enable precise and selective removal of unwanted material, while preserving the integrity of the target region of interest. We demonstrate the effectiveness of our approach on various advanced packages and show how it facilitates the failure analysis tasks for HPC chips.

For decades, device scaling has been the primary driver of the performance boost in integrated circuit (IC) devices. However, this trend has slowed down in recent years due to physical limitations and technical challenges. To continue meeting the ever-increasing demand for high-performance computing, other innovations such as advanced transistor designs and packaging schemes have emerged. Advanced transistors, such as FinFETs and Gate-all-around FET (GAAFETs), have been developed to overcome the limitations of traditional planar transistors, offering higher performance and energy efficiency. Meanwhile, advanced packaging schemes, such as system-in-package (SiP), 2.5D, and 3D packaging, offer higher integration densities, improved thermal management, and faster data transmission. These innovations are crucial in driving the development of high-performance computing, and they will play an essential role in meeting the growing demand for faster and more efficient computing.

This paper demonstrates a novel defect localization approach based on EBIRCH isolation conducted from the backside of flip chips. It discusses sample preparation and probing considerations and presents a case study that shows how the technique makes it possible to determine the root cause of subtle defects, such as bridging, in flip chip failures.

A typical workflow for advanced package failure analysis usually focuses around two key sequential steps: defect localization and defect characterization. Defect localization can be achieved using a number of complementary techniques, but electro optical terahertz pulse reflectometry (EOTPR) has emerged as a powerful solution. This paper shows how the EOTPR approach can be extended to provide solutions for the growing complexity of advanced packages. First, it demonstrates how localization of defects can be performed in traces without an external connection, through the use of an innovative cross-sectional probing with EOTPR. Then, the paper shows that EOTPR simulation can be used to extract the interface resistance, granting an alternative way of quantitative defect characterization using EOTPR without the destructive physical analysis. These novel approaches showed the great potential of EOTPR in failure analysis and reliability analysis of advanced packaging.

This paper demonstrates a methodology for chip level defect localization that allows complex logic nets to be approached from multiple perspectives during failure analysis of modern flip-chip CMOS IC devices. By combining chip backside deprocessing with site-specific plasma Focused Ion Beam (pFIB) low angle milling, the area of interest in a failure IC device is made accessible from any direction for nanoprobing and Electron Beam Absorbed Current (EBAC) analysis. This methodology allows subtle defects to be more accurately localized and analyzed for thorough root-cause understanding.

This paper introduces a novel sample preparation method using plasma focused ion-beam (pFIB) milling at low grazing angle. Efficient and high precision preparation of site-specific cross-sectional samples with minimal alternation of device parameters can be achieved with this method. It offers the capability of acquiring a range of electrical characteristic signals from specific sites on the cross-section of devices, including imaging of junctions, Fins in the FinFETs and electrical probing of interconnect metal traces.

This paper presents backside physical failure analysis methods for capturing anomalies and defects in advanced flip-chip packaged, bulk silicon CMOS devices. Sample preparation involves chemically removing all the silicon, including the diffusions, to expose the source/drain contact silicide and the gate of the transistors from the backside. Scanning Electron Microscopy (SEM) is used to form high resolution secondary and/or backscattered electron images of the transistor structures on and beneath the exposed surface. If no visual defects/anomalies are found at the transistor level, the Electron Beam Absorbed Current (EBAC) technique is used to isolate short/open defects in the interconnect metallization layers by landing nano-probe(s) on a transistor’s source/drain silicide or on the gate. Using the combination of secondary and backscattered electron imaging and backside EBAC thus allows defects residing in either the transistors or the metal nets to be found. Case studies from 20 nm technology node graphics processing units (GPU) are presented to demonstrate the effectiveness of this approach.

Visible Light (or Laser) Probing (VLP) is an exciting new development in Laser Voltage Probing (LVP) technology because it promises a dramatic improvement in resolution over current Near Infrared (NIR) solutions [1-3]. To have adequate visible light transmission for waveform probing and modulation mapping, however, ultrathinning of the silicon backside to <2-5 μm is required. The use of solid immersion lens (SIL) technology places additional requirements on sample preparation. In this paper, we present a simple, SIL compatible technique for VLP sample preparation.