Circuit Edit and Optical Probe technologies must scale with Intel’s 2 year process cycle and the tick-tock design model. Geometry shrinking combined with revolutionary and evolutionary process changes such-as high-k and metal gate, lower-k interlayer dielectrics, and non-planar devices, make this very challenging. To develop new tools, analytical processes, and validate if the current tool suite can analyze next generation process node and architectures, a special debug block has been designed into Intel’s process test vehicle. In this paper the authors first provide an overview of the Debug Block, we then provide an overview of the LADA, IREM, LVP, TRE, and FIB tools and their corresponding technical challenges for Intel’s next generation microprocessors. Finally we discuss the circuits, layout, and 32nm results.

Silicon microsurgery, also known as on-silicon circuit editing, has evolved into a critical capability for the ramp-up of a new microprocessor or complex integrated circuit (IC) from tapeout to production. The ability to perform edits directly on a packaged device serves two major purposes during a product’s ramp. The first is to perform in-situ verification of logic and timing related design changes, and the second is to provide engineering samples to enable further debug for system and tester level validation. In both cases, sample generation using silicon microsurgery technology can be performed in a fraction of the time it would take to tapeout a new mask layer and generate samples through the fabrication process. Silicon microsurgery techniques are also employed to assist with failure analysis. For this application, these techniques are applied to help isolate a stuck-at fault or open on a failing node. This is done by bi-passing the failure point, through signal rerouting or by performing isolation cuts to further localize the defect. This paper will review several advanced siliconmicrosurgery edit applications and supporting technologies, microsurgery RC material properties, and finally some results from 0.25 and 0.18 micron technologies.