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Jinseon Kim
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Proceedings Papers
ISTFA2023, ISTFA 2023: Conference Proceedings from the 49th International Symposium for Testing and Failure Analysis, 187-189, November 12–16, 2023,
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As memory devices decrease in dimensions, particles are found to be a major source of defects in unexpected DRAM failures due to their relatively large size. Among many DRAM defects, cross-defects account for the majority of system failures for a long time. Hard cross-defects are frequently observed in the first test step. Most of these defective cells are repaired with row or column redundancy resources. However, after high voltage and temperature stress, some of the cross-defects can additionally spread to adjacent rows or columns with reduced resistance. Recently, a new type of bridge cross-defect accompanied by row failures has emerged. This can be detected electrically through current measurements of 2 wordline (WL) under active mode. But, these defects are not obvious even after both high temperature and voltage stress. The bridge causes intermittent failure in the row-direction during DRAM operation. This soft 2-WL bridge is considered a serious fault source that can cause uncorrectable error (UE) at the system level even though on-die error correction code (ODECC) is introduced. Therefore, it is very important to find, improve, and develop control methods on such defects for future DRAM enhancement. In this paper, 2-WL defects or extended cross-defect were intensively analyzed through electrical failure analysis (eFA) and physical FA (pFA). Results reveal fine particles as the cause.
Proceedings Papers
ISTFA2022, ISTFA 2022: Conference Proceedings from the 48th International Symposium for Testing and Failure Analysis, 362-364, October 30–November 3, 2022,
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DRAM is a type of memory that stores each bit of data in a capacitor cell, leakage current is a very important electrical parameter to retain data. Therefore, larger cell capacitance and smaller leakage current have been regarded as key factors in continuous shrinkage of DRAM. Generally, gate induced drain leakage (GIDL) and junction leakage of cell transistor (CTR) are well-known, but our approach is focused on retention failure by bulk trap. In order to electrically observe the influence of bulk trap, we used the adjacent gate of CTR to control electron migration. Results show that there are many failure cells due to bulk trap, and dimension shrinkage accelerates this failure. Consequently, balancing among electrical bias point and transistor manufacturing process should be carefully considered with bulk traps.
Proceedings Papers
ISTFA2018, ISTFA 2018: Conference Proceedings from the 44th International Symposium for Testing and Failure Analysis, 138-140, October 28–November 1, 2018,
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Reduced noise immunity due to dimensional shrinkage, lower operational voltages and increasing densities results in increased soft or random failures. In practice, noises are generated by complex operation of device. In Dynamic Random Access Memory (DRAM), failures by noise are regarded as either decrease in charge at cell capacitor or increase in systematic interferences. Simple equivalent circuit of One Transistor One Capacitor (1T1C) DRAM and theoretical approach in time-domain are provided for quantitative noise analysis related to sense amplifier circuitries. Results show that local voltage fluctuation reduces sensing margin to judge data-0 or data-1. This phenomenon is easily observed at 1T1C with high resistance because response of voltage generator is comparatively slow.
Proceedings Papers
ISTFA2017, ISTFA 2017: Conference Proceedings from the 43rd International Symposium for Testing and Failure Analysis, 424-426, November 5–9, 2017,
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For fault management, various types of error-correcting codes (ECC) have been widely used for most computers and memory. From a memory perspective, the ECC technique is generally adopted for DRAM modules to correct data corruption among multiple chips, not in-chip level. Recently, increased soft single-bit failures have accelerated introduction of the ECC technique into DRAM components. For reliability, fault generation technique by high voltage at high temperature, also known as burn-in stress, has been widely used in the IC manufacturing process. In DRAM, burn-in stress is also useful to screen latent defects or to predict device lifetime. In this paper, we studied un-correctable errors which occurred due to various types of storage node bridge defects in ECC DRAM. 12 faulty cells among 1,000 cells are observed after burn-in stress. Retention time of each cell is measured with automatic test equipment under the various temperature conditions, and activation energy were extracted from measurement results. Results of activation energy show that there were two types of faults, one was metal-metal hard bridge (0.14eV) and the other was dielectric-dielectric soft bridge (0.35eV), in comparison with normal cells (0.53eV). Moreover, soft bridge was carefully analyzed with TEM and nanoprobing showing that activation energy analysis was well-matched.
Proceedings Papers
ISTFA2016, ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis, 82-84, November 6–10, 2016,
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System failure due to a progressive defect in memory cell-array of DRAM was studied with automated test equipment. In order to find out relationship correctable single-bit fault and system failure, memory cells with single-bit fault by a cross-defect were selected. After high voltage and temperature stress, a soft cross-defect was changed into a hard cross-defect. Consequentially, invalid operation by a degraded cross-defect causes array-failure. Based on the failure analysis, methods to prevent array-failure are proposed, and applied to DRAM successfully.