The standard requirement for FA Engineers needing to remove components from a board, prior to decapsulation or sample preparation, is shown to be greatly reduced, by the methods discussed here. By using a mechanical selected area preparation system with an open-design it is possible to reach all required areas of a large printed circuit board (PCB) or module to prepare a single component ‘in situ’. This makes subsequent optical or electrical testing faster and often more convenient to accomplish. Electronic End-pointing and 3D curvature compensation methods can often be used in parallel with sample prep techniques to further improve the consistency and efficacy of the decapsulation and thinning uniformity and final remaining silicon thickness (RST). Board level prep eliminates the worry of rework removal of BGA packages and the subsequent risk of damage to the device. Since the entire board is mounted, the contamination is restricted to the die surface and can be kept from the underside ball connections unlike current liquid immersion methods of package thinning or delayering. Since the camera is in line with the abrasion interface, imaging is real time during the entire milling and thinning process. Recent advances in automated tilt-table design have meant that a specific component’s angular orientation can be optimized for sample preparation. Improved tilt table technology also allows for improved mounting capability for boards of many types and sizes. The paper describes methods for decapsulation, thinning and backside polishing of a part ‘in situ’ on the polishing machine and allows the system to operate as a probe station for monitoring electrical characteristics while thinning. Considerations for designing board-level workholders are described – for boards that that are populated with components on one or even both sides. Using the techniques described, the quality of sample preparation and control is on a par with the processing of single package-level devices.

Interactive electrical endpoint detection when thinning conductive and capacitive materials opens the door to approaching a suspect site in an IC without relying on the traditional iterative approach. Controlled approach of embedded conductors in insulators (packages) as well as controlled die thinning with submicron control will be shown, allowing safe approach to the desired feature without overshoot.

Backside sample preparation is required by many post silicon validation techniques like FIB (Focused Ion Beam) circuit editing and optical probing using Photon Emission or Laser Stimulus methods [1]. In spite of many conventional methods of silicon thinning and polishing, some challenges remain as new packages are introduced. With large die packages the issue of cracking during backside thinning is arising due to package curvature stress. 3D profile methods will be shown in conjunction with thermal relaxation to alleviate silicon center to edge variance allowing sample prep of large areas with thicknesses below 10μm. Thinning and polishing methods will be shown to be interactive with the device heated; demonstrating both thermal stress reduction coupled with curvature reduction.

In the field of failure analysis of integrated circuits, diagnosing functional failures is a requirement. Traditional beam-based analysis techniques use a scanning laser or ebeam to induce a parametric shift, which is monitored through changes in current or voltage driven to the device. Deep submicron technologies frustrate these analytical methods due to the nearly immeasurable parametric shifts externally caused by a small signal leakage path internally. These internal failures can be identified functionally by timing, temperature or voltage dependencies but the exact location of the fault is difficult to isolate. SIFT (Stimulus Induced Fault Test), RIL (Resistive Interconnect Localization) and SDL (Soft Defect Localization) can identify anomalies functionally using induced thermal gradients to the metal but does not address how to analyze embedded temperature sensitive defects inaccessible to the laser. 1,2,3,4 Stacked die and similar 3 dimensional (3D) devices complicate the analysis requiring destruction/removal of one or more die. This paper will show how to create quantifiable thermal gradients to a defect and triangulate the location of the defect in 1, 2, and 3 dimensions as follows: 1. Apply a differential temperature gradient across the device in each of the X,Y, and Z-axes. The defect is localized based on its measured response in the gradient as the gradient sweeps across. 2. Induce a gradient with a laser and use the measurement of DC power required to relate the distance to the defect from various locations in relation to a heat sink. 3. Measure the time of flight of the thermal propagation to a defect from known laser positions to triangulate the location of the defect.

Photovoltaic devices (PV) or more commonly “solar cells” are analyzed using LBIC/LBIV (Light Beam Induced Current/Voltage) PL (Photoluminescence) and EL (Electroluminescence) as well as INSB thermal Methods. This paper will show the advantages and pitfalls of the techniques as well as a novel way to perform EL imaging without a dark box and thermal imaging through glass panels.

In the field of failure analysis of integrated circuits, diagnosing functional failures is a requirement. Traditional beam-based analysis techniques use a scanning laser or e-beam to induce a parametric shift which is monitored through changes in current or voltage driven to the device. Deep submicron technologies frustrate these analytical methods due to the nearly immeasurable parametric shifts externally caused by a small signal leakage path internally. These internal failures can be identified functionally by timing, temperature or voltage dependencies but the exact location of the fault is difficult to isolate. RIL (Resistive Interconnect Localization) is a newer technique which can identify via anomalies functionally using induced thermal gradients to the metal but does not address how to uniformly inject the thermal energy required in the silicon to analyze timing design deficiencies and other defects.[1] With SIFT (Stimulus Induced Fault Testing), numerous stimuli will be used to identify speed, fault, and parametric differences in silicon. The heart of this technique revolves around intentionally disturbing devices with external stimuli and comparing the test criteria to reference parts or timing/voltage sensitivities. Synchronous interfacing is possible to any tester without any wiring or program changes.