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1-6 of 6
Jie Zhu
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Proceedings Papers
ISTFA2014, ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis, 227-230, November 9–13, 2014,
Abstract
View Papertitled, Understanding the Cu Void Formation by TEM Failure Analysis
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for content titled, Understanding the Cu Void Formation by TEM Failure Analysis
In this work, we present TEM failure analysis of two typical failure cases related to metal voiding in Cu BEOL processes. To understand the root cause behind the Cu void formation, we performed detailed TEM failure analysis for the phase and microstructure characterization by various TEM techniques such as EDX, EELS mapping and electron diffraction analysis. In the failure case study I, the Cu void formation was found to be due to the oxidation of the Cu seed layer which led to the incomplete Cu plating and thus voiding at the via bottom. While in failure case study II, the voiding at Cu metal surface was related to Cu CMP process drift and surface oxidation of Cu metal at alkaline condition during the final CMP process.
Proceedings Papers
ISTFA2014, ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis, 246-249, November 9–13, 2014,
Abstract
View Papertitled, Observation of Channel Strain Release in pMOS Device with Low Idsat Using Energy-Filtered Nano-Beam Diffraction Technique
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for content titled, Observation of Channel Strain Release in pMOS Device with Low Idsat Using Energy-Filtered Nano-Beam Diffraction Technique
In this work, energy-filtered TEM nano-beam diffraction (NBD) technique was used to evaluate channel strain profile in pMOS transistors suffering low Idsat issue. TEM and EDX analysis showed nickel deep diffusion into embedded SiGe source/drain. Such defect not only led to leakage current from S/D to substrate but might also reduce compressive strain induced to channel by eSiGe. Comparison of channel-direction strain between bad and good samples using NBD confirmed strain relaxation in bad sample which explained low Idsat as a result of reduced holes mobility.
Proceedings Papers
ISTFA2014, ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis, 413-419, November 9–13, 2014,
Abstract
View Papertitled, Application of Automated FIB for TEM Sample Preparation in Semiconductor Failure Analysis
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for content titled, Application of Automated FIB for TEM Sample Preparation in Semiconductor Failure Analysis
In this paper, we describe automated FIB for TEM sample preparation using iFast software on a Helios 450HP dual-beam system. A robust iFast automation recipe needs to consider as many variables as possible in order to ensure consistent sample quality and high success rate. Variations mainly come from samples of different materials, structures, surface patterns, surface topography and surface charging. The recipe also needs to be user-friendly and provide high flexibility by allowing users to choose preferable working parameters for specific types of samples, such as: grounding, protective layer coating, milling steps, and final TEM lamella thickness/width. In addition to the iFast recipe, other practical factors affecting automation success rate are also discussed and highlighted.
Proceedings Papers
ISTFA2014, ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis, 480-484, November 9–13, 2014,
Abstract
View Papertitled, Tri-Directional TEM Failure Analysis on Sample Prepared by In-Situ Lift-Out FIB and Flipstage
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for content titled, Tri-Directional TEM Failure Analysis on Sample Prepared by In-Situ Lift-Out FIB and Flipstage
In this paper, we report an advanced sample preparation methodology using in-situ lift-out FIB and Flipstage for tridirectional TEM failure analysis. A planar-view and two cross-section TEM samples were prepared from the same target. Firstly, a planar-view lamellar parallel to the wafer surface was prepared using in-situ lift-out FIB milling. Upon TEM analysis, the planar sample was further milled in the along-gate and cross-gate directions separately. Eventually, a pillar-like sample containing a single transistor gate was obtained. Using this technique, we are able to analyze the defect from three perpendicular directions and obtain more information on the defect for failure root-cause analysis. A MOSFETs case study is described to demonstrate the procedure and advantages of this technique.
Proceedings Papers
ISTFA2012, ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis, 356-358, November 11–15, 2012,
Abstract
View Papertitled, Tomographic Study of Silicon Nanoparticles in Nanocrystalline Non-Volatile Flash Memory Devices by EFTEM
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for content titled, Tomographic Study of Silicon Nanoparticles in Nanocrystalline Non-Volatile Flash Memory Devices by EFTEM
The distribution of Si nanoparticles, both dimensional and spatial, is a key factor affecting the performance of non-volatile flash memory devices. A new FIB method has been developed to prepare ultra-thin plan view specimens, containing only the Si nanoparticle matrix thin film layer, from fully processed nanocrystalline flash memory devices. The morphology and distribution of Si nanoparticles were then studied by EFTEM 3D tomographic reconstruction.
Proceedings Papers
ISTFA2011, ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis, 301-304, November 13–17, 2011,
Abstract
View Papertitled, Impacts of Sample Preparation Methodology on TEM Failure Analysis of Advanced Semiconductor Devices
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for content titled, Impacts of Sample Preparation Methodology on TEM Failure Analysis of Advanced Semiconductor Devices
In this paper, two failure analysis case studies are presented to demonstrate the importance of sample preparation procedures to successful failure analyses. Case study 1 establishes that Palladium (Pd) cannot be used as pre-FIB coating for SiO2 thickness measurement due to the spontaneously Pd silicide formation at the SiO2/Si interface. Platinum (Pt) is thus recommended, in spite of the Pt/SiO2 interface roughness, as the pre-FIB coating in this application. In the second case study, the dual-directional TEM inspection method is applied to characterize the profile of the “invisible” tungsten residue defect. The tungsten residue appears invisible in the planeview specimen due to the low mass-thickness contrast. It is then revealed in the cross-sectional TEM inspection.