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1-7 of 7
Jiaqi Tang
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Proceedings Papers
ISTFA2024, ISTFA 2024: Conference Proceedings from the 50th International Symposium for Testing and Failure Analysis, 58-69, October 28–November 1, 2024,
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One of the foremost challenges in the field of SiC MOSFET failure analysis is the effect of thermally modified mold compound on the decapsulation process. The extended total etch time that thermal modification imposes on the process of wet chemical decapsulation has created a niche for new techniques to fill. This paper focuses on use cases for the JIACO microwave-induced plasma (MIP) etching system and how to best optimize the tool’s settings to facilitate time-efficient decapsulations. The words and data that follow aim to present what has been determined to be a successful alternative for the decapsulation of thermally modified Si and SiC power devices when wet etches prove to be ineffective.
Proceedings Papers
ISTFA2024, ISTFA 2024: Conference Proceedings from the 50th International Symposium for Testing and Failure Analysis, 492-495, October 28–November 1, 2024,
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The rapid development of advanced packaging technologies for high-performance computing (HPC) applications poses significant challenges for sample preparation methodologies. Conventional techniques are often insufficient to cope with the complex architectures and heterogeneous materials of modern packages, such as COWOS (Chip-on-Wafer-on-Substrate) and 3D structures. In this paper, we present a novel approach for sample preparation that leverages precision CNC (Computer Numerical Control) milling and selective MIP plasma etch. These methods enable precise and selective removal of unwanted material, while preserving the integrity of the target region of interest. We demonstrate the effectiveness of our approach on various advanced packages and show how it facilitates the failure analysis tasks for HPC chips.
Proceedings Papers
ISTFA2024, ISTFA 2024: Conference Proceedings from the 50th International Symposium for Testing and Failure Analysis, 509-514, October 28–November 1, 2024,
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III-V power electronic devices are a growing industry as electric vehicles (EVs), power-demanding servers, and other high-power electronics become more prominent. The design of these devices can alter a failure analysis lab’s process flow typically used on traditional silicon-based logic devices. One such obstacle is backside fault isolation (FI) through highly doped silicon wafers used in GaN-on-Si technologies. Backside fault isolation is critical for many electrical failure analyses so finding several approaches to enable this technique that fits current FA flows is desirable. Chemical and Focused Ion Beam (FIB) based approaches have been used to enable backside FI [1], [2]. This paper considers a plasma-based approach with two separate machines, a Microwave Induced Plasma spot etcher and a chamber based Reactive Ion Etch (RIE). Both utilize a Fluorine-based chemistry which is highly selective to the silicon vs the underlying GaN. The etches are used to selective remove the silicon to form a window to the underlying GaN material. Subsequent backside FI analyses are successfully followed by several other analyses.
Journal Articles
Journal: EDFA Technical Articles
EDFA Technical Articles (2021) 23 (1): 4–10.
Published: 01 February 2021
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Several failure analysis case studies have been conducted over the past few years, illustrating the importance of preserving root-cause evidence by means of artifact-free decapsulation. The findings from three of those studies are presented in this article. In one case, the root cause of failure is chlorine contamination. In another, it is a combination of corrosion and metal migration. The third case involves an EOS failure, the evidence of which was hidden under a layer of carbonized mold compound. In addition to case studies, the article also includes images that compare the results of different decapsulation methods.
Proceedings Papers
ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 226-232, November 15–19, 2020,
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Advanced packages such as 2.5D will continue to grow in demand as performance increases are needed in various applications. Failure analysis must adapt to the changes in the interfaces, materials and structures being developed and now utilized. Traditional techniques and tools used for selectively removing materials to isolate and analyze defects need to evolve alongside these packages. A CF4-free Microwave Induced Plasma (MIP) process is used to remove underfill (UF) with minimal alteration of other materials on the samples, a process which has become more difficult on 2.5D modules. UF is removed using this MIP process to allow subsequent analysis on interposer interconnects and ìbumps in crosssection. SEM inspection, Electron Beam Absorbed Current (EBAC), and FIB are techniques used post cross-sectional UF removal of these 2.5D structures. The benefits of the specific MIP process through case studies are presented. Specifically, the use of an automatic cleaning step and a CF4-free downstream O2 plasma allow easy removal of UF without damaging other structures of interest with little tool recipe development.
Proceedings Papers
ISTFA2016, ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis, 151-160, November 6–10, 2016,
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Failure analysis of automotive semiconductor devices requires highly reliable techniques to guaranty the success of artifact-free decapsulation with high repeatability and reproducibility. With the introduction of new qualification standards, new mold compounds, and new packaging structures, advanced decapsulation tools are needed to enable failure analysis to achieve a high success rate. Microwave Induced Plasma (MIP) machine has been developed as an advanced decapsulation solution. The CF4-free MIP etching ensures artifact-free exposure of bond wires made of new materials, the die, passivation, bond pads, and original failure sites. The high mold compound etching rate, high etching selectivity of mold compound to wire/pad/passivation/die, and the fully automatic process are the unique features of MIP decapsulation. Comparisons are made between acid, conventional plasma with CF4, and CF4-free MIP decapsulation. Multiple case studies are discussed that address challenging automotive semiconductor device decapsulation, including bare copper wire, copper redistribution layer, exposed power copper metal, stitch bond on silver plated leadframe, complex mold compound, Bond-Over-Active-Circuit, eWLB, and localized decapsulation.
Proceedings Papers
ISTFA2015, ISTFA 2015: Conference Proceedings from the 41st International Symposium for Testing and Failure Analysis, 480-490, November 1–5, 2015,
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With the introduction of new packaging technologies and the great variety of semiconductor devices, new decapsulation tools are needed to improve failure analysis with a higher success rate, and to improve quality control with a higher confidence level. Conventional downstream microwave plasma etchers use CF4 or other fluorine containing compounds in the plasma gas that causes unwanted overetching damage to Si3N4 passivation and the Si die, thus limiting its use in IC package decapsulation. The approach of atmospheric pressure O2-only Microwave Induced Plasma (MIP) successfully solves the fluorine overetching problem. Comparison between MIP, conventional plasma, acid etching based on several challenging decapsulation applications has shown the great advantage of MIP in preserving the original status of the die, wire bonds, and failure sites. One of the challenging failure analysis cases is Bond-Over-Active-Circuit (BOAC) devices with exposed thin copper metallization traces on top of Si3N4 passivation. The BOAC critical die structures present a challenge to both conventional plasma and acid decapsulation. The use of MIP to solve the BOAC device decapsulation problem will be discussed in detail through multiple case studies. It appears that the MIP machine is the only approach to decapsulate BOAC devices without causing any damage to the exposed copper on passivation critical structure, which demonstrates the failure analysis capabilities of the MIP system.