Transmission electron microscopy (TEM) plays an important role in the structural analysis and characterization of materials for process evaluation and failure analysis in the integrated circuit (IC) industry as device shrinkage continues. It is well known that a high quality TEM sample is one of the keys which enables to facilitate successful TEM analysis. This paper demonstrates a few examples to show the tricks on positioning, protection deposition, sample dicing, and focused ion beam milling of the TEM sample preparation for advanced DRAMs. The micro-structures of the devices and samples architectures were observed by using cross sectional transmission electron microscopy, scanning electron microscopy, and optical microscopy. Following these tricks can help readers to prepare TEM samples with higher quality and efficiency.

This paper is to evaluate the doping profile analysis capability of Scanning Capacitance Microscope (SCM) and Scanning Spreading Resistance Microscope (SSRM) on 30nm Dynamic Random Access Memory (DRAM) devices and apply the SSRM technique on a real case to verify the junction depths of different doping recipes for device performance tuning. The results show SCM can be used on periphery devices in a 30nm DRAM due to they have larger feature size (>90nm). For array devices with minimum feature size (~30nm) in a 30nm DRAM, only SSRM is capable with sufficient spatial resolution and sensitivity to identify the structures and doping profiles. For the real case, SSRM analysis results clarified there is approximate 10nm difference on the junction depth between 2 different doping recipes of samples and the result is consistent with the Technology Computer Aided Design (TCAD) simulation data. In addition, both SCM and SSRM techniques showed the analysis quality does highly rely on the surface cleanness and flatness of samples.

Several methods are used to invert samples 180 deg in a dual beam focused ion beam (FIB) system for backside milling by a specific in-situ lift out system or stages. However, most of those methods occupied too much time on FIB systems or requires a specific in-situ lift out system. This paper provides a novel transmission electron microscopy (TEM) sample preparation method to eliminate the curtain effect completely by a combination of backside milling and sample dicing with low cost and less FIB time. The procedures of the TEM pre-thinned sample preparation method using a combination of sample dicing and backside milling are described step by step. From the analysis results, the method has applied successfully to eliminate the curtain effect of dual beam FIB TEM samples for both random and site specific addresses.

In this paper, we revealed p+/n-well and n+/p-well junction characteristic changes caused by electron beam (EB) irradiation. Most importantly, we found a device contact side junction characteristic is relatively sensitive to EB irradiation than its whole device characteristic; an order of magnitude excess current appears at low forward bias region after 1kV EB acceleration voltage irradiation (Vacc). Furthermore, these changes were well interpreted by our Monte Carlo simulation results, the Shockley-Read Hall (SRH) model and the Generation-Recombination (G-R) center trap theory. In addition, four essential examining items were suggested and proposed for EB irradiation damage origins investigation and evaluation. Finally, by taking advantage of the excess current phenomenon, a scanning electron microscope (SEM) passive voltage contrast (PVC) fault localization application at n-FET region was also demonstrated.

This paper demonstrated the use of curve fitting method on device transfer characteristic curve for device carrier mobility analysis and failure mechanism verification. In the content, a systematic device characterization was performed to identify device failure mode and failure site. Based on physical observations and electrical results, a device gate oxide boron penetration failure mechanism and an unexpected subtle p-type dopant at p-MOS device channel area was conjectured. However, this unexpected p-type dopant was successfully proved by subsequent carrier mobility analysis results, and the gate oxide boron penetration failure mechanism was accordingly verified.

This paper presents the memory cell level passive voltage contrast (PVC) involving diode, capacitor and transistor devices in a (dynamic random access) DRAM chip. More particularly, we show that the voltage contrast sensitivity can be improved significantly by the adjustment of scan location and scan location sequence. Both leaky and resistive fault localizations by PVC imaging are presented to illustrate our point.

Owing to the limitations of physical failure analysis (FA) techniques and fault localization techniques, the nano-probing tool, which has both the device characterization ability as well as the necessary sensitivity to characterize the non-visible defects and marginal fails, has emerged to be a powerful tool in the FA community. This paper presents a nano-probing technique on two yield impact cases in dynamic random access memory technology. The first case is related to a die that exhibited a high pin current issue during the parametric test sequence at the early stage of our probe test. The second case is related to a column fail expanding across a shared sense amplifier (SA) circuit. By comparing the nano-probing electrical results with simulation data and wafer acceptance test data, insufficient (S/D) contact implant which causes slower p-MOS turn-on and resistive source contact that causes lower driving ability in a SA transistor issue are concluded.

The use of in-situ lift-out combined with focused ion beam milling has become a favorable choice as it offers several indispensable advantages compared to the conventional mechanical and ex-situ lift-out sample preparation techniques. This paper discusses the procedures of the multiple-post in-situ lift-out grids preparation using a dicing saw. In addition, a real case is described to show that the multiple-post in-situ lift-out grids have been successfully applied to failure analysis. The multiple-post in-situ lift-out grids provide more positions and flatter surfaces for TEM sample mounting. The flat surface greatly increases the mounting efficiency and success rate. For the real case application, a thick Al fluoride oxide layer and Al corrosion were found above the Al bond pads, which had NOSP problem, and their neighbor area, respectively.

This paper provides details of a novel method developed to cover a tiny epoxy layer as an intermediate buffer on the site-specific surface defect using a micro-bush on the tip of a glass needle in a plucking system without sample surface damage and localization problems. It describes the method and some real cases. The microstructures are investigated using an FEI Tecnai TF20 field emission gun transmission electron microscopy equipped with a high angle annular dark field detector, an energy dispersive X-ray spectroscopy, and Gatan image filter systems. The paper explains the micro-brushes and buffer layer preparation though figures and illustrations.

Electron tomography includes four main steps: tomography data acquisition, image processing, 3D reconstruction, and visualization. After acquisition, tilt-series alignments are performed. Two methods are used to align the tilt-series: cross-correlation and feature tracking. Normally, about 10-20 nm of fiducial markers, such as gold beads, are deposited onto one side of 100 mesh carbon-coated grids during the feature-tracking process. This paper presents a novel method for preparing electron tomography samples with gold beads inside to improve the feature tracking process and quality of 3D reconstruction. Results show that the novel electron tomography sample preparation method improves image alignment, which is essential for successful tomography in many contemporary semiconductor device structures.

It is well known that pursuing the miniaturization of devices to lower the cost and increase high-speed performance are extremely important goals for dynamic random access memory (DRAM). Therefore, electron tomography has a high potential for application to novel generation DRAMs. In this article, several real-case examples of electron tomography on 90 nm technology DRAM, including barrier layer step coverage, via fill process observations and defect analysis are reported. These cases were demonstrated to show the applications of bright field-transmission electron microscope (BF-TEM) and HADDF- scanning transmission electron microscope (STEM) tomography to analyze barrier layer step coverage, defects, and W fill quality in advanced DRAM. By appropriate use of BF-TEM or HAADF STEM tomography, optimal information for failure analysis, root cause clarification, and subsequent process improvements can be obtained. Electron tomography holds significant advantages in comparison to traditional TEM imaging for appropriate cases.

This paper demonstrates a novel method of XTEM sample preparation for site-specific surface defect analysis using backside polishing. Analysis of three different types of site-specific surface defects was demonstrated using a novel backside XTEM sample preparation method. The details of the backside XTEM sample preparation method and some examples are reported in this paper. Comparing to Auger electron spectrometry (AES) results on similar defects, more detailed and precise information is observed using TEM analysis with this method. It is therefore a complementary technique to traditional AES analysis on surface defects for contamination with atomic level concentration. From the results, the sample preparation method can produce a clean, pristine surface that is well characterized and could be reproduced, successfully.

The capabilities of analytical transmission electron microscopy (TEM), such as high spatial resolution, micro-chemical analysis, etc., have led to an increasingly essential role for TEM-based analysis in process development, defect identification, yield enhancement, and root-cause failure analysis with the dynamic random access memory (DRAM) industry. In this article, several examples are reported to carry out the applications of TEM and secondary ion mass spectrometry on crystal defect analysis and electronic characteristics of advanced 512 Mb DRAMs.

X-ray photoelectron spectroscopy (XPS) is a very popular tool for identification of the chemical state of fluorine contamination on aluminum (Al) bond pads. To date, as far as the authors are aware the detailed microstructures of fluorine corrosion on bond pads have not been reported. This paper reports the microstructure evolution of fluorine corrosion on bond pads in a plastic box under specific environment conditions by using transmission electron microscopy (TEM), optical microscopy, focused ion beam and scanning electron microscopy (SEM). The elemental distributions and chemical bonding were performed by using Gatan Image Filter/TEM, energy dispersive X-ray/Scanning TEM (STEM), Auger electron spectroscopy and XPS, respectively. On Al pads with 35 atomic %, fluorine residual, corrosion was observed after around 10 days of storage and became more severe with time. The corrosion layers consist of nano-crystalline and amorphous for both single and double-layer structures.

Application of the high resolution of Transmission Electron Microscopy (HRTEM) plays a very important role in structural analysis and materials characterization for process evaluation and failure analysis in the Integrated Circuit (IC) industry. We summarize TEM observation experience of the common memory failures of a BEST deep trench cell with an N-MOS gate used in CMOS DRAM technology. Memory cell failures are categorized into three areas for discussion – the deep trench (DT) capacitor, the transfer gate (GC), and the borderless bit-line contact (CB) between a transistor and a bit line. Typical examples that occurred in these three areas are presented and provide a basic understanding of normal DRAM cell failures.

Three techniques have been developed for TEM sample preparation to improve efficiency in terms of time reduction and success rate. The first technique is to closely control the thickness of a sample for a specific area to less than 10µm by mechanical polishing before undergoing FIB thinning. The second one is to repair cracks produced during mechanical polishing before further milling in the ion miller. The last one is to provide an in-FIB remedy for face-to-face cross-sectional samples, which peel from each other during mechanical polishing. These new techniques will substantially enhance the success rate and turnaround time for TEM sample preparation.