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1-7 of 7
Jian Chang Lin
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Proceedings Papers
ISTFA2014, ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis, 304-306, November 9–13, 2014,
Abstract
View Papertitled, Defect Localization and Root Cause Analysis on e-Fuse Read Reliability Failure
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for content titled, Defect Localization and Root Cause Analysis on e-Fuse Read Reliability Failure
Fault isolation is the most important step for Failure Analysis (FA), and it is closely linked with the success rate of failure mechanism finding. In this paper, we will introduce a case that hard to debug with traditional FA skills. In order to find out its root cause, several advanced techniques such as layout tracing, circuit edit and Infrared Ray–Optical Beam Induced Resistance Change (IR-OBIRCH) analysis had been applied. The circuit edit was performed following layout tracing for depositing probing pads by Focused Ion Beam (FIB). Then, IR-OBIRCH analysis with biasing on the two FIB deposited probing pads and a failure location was detected. Finally, the root cause of inter- metal layer bridge was found in subsequent physical failure analysis.
Proceedings Papers
ISTFA2011, ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis, 399-402, November 13–17, 2011,
Abstract
View Papertitled, Novel Gox Inspection Methodology in Advanced Silicon Process
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for content titled, Novel Gox Inspection Methodology in Advanced Silicon Process
This paper describes a new gate oxide (Gox) inspection method that uses nanoprobing and capacitive-atomic force microscopy (C-AFM) along with optimized etch chemistries and polishing techniques. It presents several examples showing how the new method outperforms conventional Gox inspection approaches in its ability to locate defects such as oxide pin holes and impurities that cause leakage current. It also discusses the electrical behavior of pin holes and soft defects.
Proceedings Papers
Using Nano-Probing Technique to Clarify Nickel Silicide beyond Process Window Causing Device Failure
ISTFA2010, ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis, 236-238, November 14–18, 2010,
Abstract
View Papertitled, Using Nano-Probing Technique to Clarify Nickel Silicide beyond Process Window Causing Device Failure
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for content titled, Using Nano-Probing Technique to Clarify Nickel Silicide beyond Process Window Causing Device Failure
A scanning electron microscopy (SEM) based nano-probing system is used in this study to clarify nickel silicide phase beyond process window. According to the nano-probing measurement result and the cross-sectional transmission electron microscopy (TEM) images, phenomena of junction leakage along with high resistance and a larger nickel silicide area are observed at failure site at the same time. The type of failure mechanism and in-line process issue caused multiple failure phenomena at failure site will be the major focuses in this paper. Nickel silicide phase transformation from NiSi to NiSi2 is highly suspected by the comparison of sheet resistance and silicon consumption. Consequently, nickel silicide beyond process window could be verified immediately.
Proceedings Papers
ISTFA2009, ISTFA 2009: Conference Proceedings from the 35th International Symposium for Testing and Failure Analysis, 230-233, November 15–19, 2009,
Abstract
View Papertitled, A Novel Technique of Device Measurement after Cross-Sectional FIB in Failure Analysis
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for content titled, A Novel Technique of Device Measurement after Cross-Sectional FIB in Failure Analysis
A dual beam FIB (Focused Ion Beam) system which provides the ion beam (i-beam) and electron beam (e-beam) function are widely used in semiconductor manufacture for construction analysis and failure cause identification. Although FIB is useful for defect or structure inspection, sometimes, it is still difficult to diagnose the root cause via FIB e-beam image due to resolution limitation especially in products using nano meter scale processes. This restriction will deeply impact the FA analysts for worst site or real failure site judgment. The insufficient e-beam resolution can be overcome by advanced TEM (Transmission Electron Microscope) technology, but how can we know if this suspected failure site is a real killer or not when looking at the insufficient e-beam images inside a dual beam tool? Therefore, a novel technique of device measurement by using C-AFM (Conductive Atomic Force Microscope) or Nano-Probing system after cross-sectional (X-S) FIB inspection has been developed based on this requirement. This newly developed technology provides a good chance for the FA analysts to have a device characteristic study before TEM sample preparation. If there is any device characteristic shift by electrical measurement, the following TEM image should show a solid process abnormality with very high confidence. Oppositely, if no device characteristic shift can be measured, FIB milling is suggested to find the real fail site instead of trying TEM inspection directly.
Proceedings Papers
ISTFA2007, ISTFA 2007: Conference Proceedings from the 33rd International Symposium for Testing and Failure Analysis, 172-175, November 4–8, 2007,
Abstract
View Papertitled, A Case Study of Defects Due to Process-Design Interaction in Nano Scale Technology
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for content titled, A Case Study of Defects Due to Process-Design Interaction in Nano Scale Technology
The difficulties in identifying the precise defect location and real leakage path is increasing as the integrated circuit design and process have become more and more complicated in nano scale technology node. Most of the defects causing chip leakage are detectable with only one of the FA (Failure Analysis) tools such as LCD (Liquid Crystal Detection) or PEM (Photon Emission Microscope). However, due to marginality of process-design interaction some defects are often not detectable with only one FA tool [1][2]. This paper present an example of an abnormal power consumption process-design interaction related defect which could only be detected with more advanced FA tools.
Proceedings Papers
ISTFA2006, ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis, 208-213, November 12–16, 2006,
Abstract
View Papertitled, A Fast Inspection of Well Implantation by Using Plane-View Stain Method
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for content titled, A Fast Inspection of Well Implantation by Using Plane-View Stain Method
In the field of failure analysis, electrical failures caused by improper implantation are often difficult to debug especially for fully processed products. Familiar implantation failure issues include improper implantation concentration, error doping types, incorrect doping ranges, and etc. Although some FA equipments, such as secondary ion mass spectrometry (SIMS), spreading resistance probe (SRP) and scanning capacitance microscope (SCM) [1] [2] [3], can do detail or quantitative analysis for these failure issues, most of these FA jobs are time-consuming and have a detection limitation at the size of failure area. This limitation may restrict the FA applications because the failure area is usually small at the fully processed products after fault isolation. In this paper, two examples with improper doping type and concentration will be analyzed by using a newly developed FA method. Instead of using traditional cross-section (X-S) stain method, we utilize a plane-view stain method to compare the doping type and doping concentration between normal and failed regions. With the aid of the plane-view stain method, we can have a quick check at the suspected failure area with improper front-end implantation before specific SCM analysis.
Proceedings Papers
ISTFA2004, ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis, 109-114, November 14–18, 2004,
Abstract
View Papertitled, Investigation of Substrate Dislocation Induced Bit Line Soft Failure
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for content titled, Investigation of Substrate Dislocation Induced Bit Line Soft Failure
In modern integrated circuits (IC) using sub-micron or deep sub-micron process rules, substrate dislocation is a common failure mechanism in SRAM or embedded SRAM products. Depending on the position of substrate dislocation in the SRAM cell, it may result in problems including junction or contact leakage, gate oxide early breakdown, low threshold voltage, and poor data retention. In this paper, we’ll focus on the test methodology and physical failure analysis to dig out the failure mechanism, substrate dislocation under SRAM pass gate and node contact. In addition, we will measure the electrical behavior of such substrate dislocation. Several FA techniques, such as Passive Voltage Contrast (PVC) [1] pad deposition by Focus Ion Beam (FIB), and electrical micro probing [2] will be used during leakage verification and measurement.